A Practical Approach to VLSI System on Chip (SoC) Design

1. Front Matter

   Pages i-xxxii

   PDF

2. Introduction

   • Veena S. Chakravarthi

   Pages 1-10

3. System on Chip (SOC) Design

   • Veena S. Chakravarthi

   Pages 11-40

4. SOC Constituents

   • Veena S. Chakravarthi

   Pages 41-61

5. VLSI Logic Design and HDL

   • Veena S. Chakravarthi

   Pages 63-80

6. SOC Synthesis

   • Veena S. Chakravarthi

   Pages 81-97

7. Static Timing Analysis (STA)

   • Veena S. Chakravarthi

   Pages 99-116

8. SOC Design for Testability (DFT)

   • Veena S. Chakravarthi

   Pages 117-139

9. SOC Design Verification

   • Veena S. Chakravarthi

   Pages 141-172

10. SOC Physical Design

    • Veena S. Chakravarthi

    Pages 173-199

11. SOC Physical Design Verification

    • Veena S. Chakravarthi

    Pages 201-214

12. SOC Packaging

    • Veena S. Chakravarthi

    Pages 215-224

13. Reference Designs

    • Veena S. Chakravarthi

    Pages 225-303

14. Back Matter

    Pages 305-312

    PDF

This book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs.

• A comprehensive practical guide for VLSI designers;
• Covers end-to-end VLSI SoC design flow;
• Includes source code, case studies, and application examples.

• VLSI-SoC
• Clock Tree synthesis
• Embedded Memory
• Embedded processor
• Embedded systems
• Fabless design
• Integrated circuits
• Memory compiler
• SOC design
• Semiconductor
• Standard cell library
• Static timing Analysis
• Very Large Scale Integration
• UPF flow
• VLSI
• System-on-Chip

• Sensesemi Technologies Private Limited, Bangalore, India

  Veena S. Chakravarthi

Dr. Veena S. Chakravarthi has more than two decades of semiconductor industry experience in managing design and development of large multiprocessor SoCs, with around six multimillion gate tape outs to her credit. She obtained her PhD in Electronics Engineering from Bangalore University in 2008. Dr. Chakravarthi is co-founder and Chief Technology Officer of Sensesemi Technologies, a healthcare startup based in Bangalore. Prior to that, she has worked for ITI Limited, Mindtree Consulting Pvt. Ltd., Centillium India Pvt. Ltd., and Transwitch India Pvt. Ltd., and consulted for Ikanos Communications, Pereira Ventures, and Asarva Chips and Technologies in various capacities. She has published many papers and filed two patents in the area of VLSI and healthcare. She has been associated with the research center in the Electronics & Communication Engineering Department at BNM Institute of Technologies, Bangalore. Her areas of research interest include low-power high performance SOCdesigns in EPON, communication, and wireless technologies. She is currently Vice Chair of the Bangalore Section Chapter of the IEEE Nanotechnology Council, and organized many events including the recent IISc IEEE Nanotechnology Summer School in July 2018.

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