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  • © 1998

Formal Equivalence Checking and Design Debugging

Part of the book series: Frontiers in Electronic Testing (FRET, volume 12)

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Table of contents (11 chapters)

  1. Front Matter

    Pages i-xviii
  2. Introduction

    1. Introduction

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 1-14
  3. Equivalence Checking

    1. Front Matter

      Pages 15-15
    2. Symbolic Verification

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 17-37
    3. Incremental Verification for Combinational Circuits

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 39-60
    4. Incremental Verification for Sequential Circuits

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 61-90
    5. AQUILA: A Local BDD-based Equivalence Verifier

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 91-109
    6. Algorithm for Verifying Retimed Circuits

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 111-121
    7. RTL-to-Gate Verification

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 123-136
  4. Logic Debugging

    1. Front Matter

      Pages 137-137
    2. Introduction to Logic Debugging

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 139-157
    3. ErrorTracer: Error Diagnosis by Fault Simulation

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 159-174
    4. Extension to Sequential Error Diagnosis

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 175-187
    5. Incremental Logic Rectification

      • Shi-Yu Huang, Kwang-Ting Cheng
      Pages 189-209
  5. Back Matter

    Pages 211-229

About this book

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley

Authors and Affiliations

  • National Semiconductor Corporation, USA

    Shi-Yu Huang

  • University of California, Santa Barbara, USA

    Kwang-Ting (Tim) Cheng

Bibliographic Information

Buy it now

Buying options

eBook USD 149.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 199.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 199.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access