VLSI for Artificial Intelligence and Neural Networks

1. Analogue and Pulse Stream Neural Networks

   1. Fully Cascadable Analogue Synapses Using Distributed Feedback

      • Donald J. Baxter, Alan F. Murray, H. Martin Reekie

      Pages 205-213

   2. Results from Pulse-Stream VLSI Neural Network Devices

      • Michael Brownlow, Lionel Tarassenko, Alan Murray

      Pages 215-224

   3. Working Analogue Pulse-Firing Neural Network Chips

      • Alister Hamilton, Alan F. Murray, H. Martin Reekie, Lionel Tarassenko

      Pages 225-233

   4. Pulse-Firing VLSI Neural Circuits for Fast Image Pattern Recognition

      • Stephen Churcher, Alan F. Murray, H. Martin Reekie

      Pages 235-244

   5. An Analog Circuit with Digital I/O for Synchronous Boltzmann Machines

      • Patrick Garda, Eric Belhaire

      Pages 245-254

2. Digital Implementations of Neural Networks

   1. The VLSI Implementation of the ∑ Architecture

      • S. R. Williams, J. G. Cleary

      Pages 255-263

   2. A Cascadable VLSI Architecture for the Realization of Large Binary Associative Networks

      • Werner Poechmueller, Manfred Glesner

      Pages 265-274

   3. Digital VLSI Implementations of an Associative Memory Based on Neural Networks

      • Ulrich Rückert, Christian Kleerbaum, Karl Goser

      Pages 275-284

   4. Probabilistic Bit Stream Neural Chip: Implementation

      • Max van Daalen, Pete Jeavons, John Shawe-Taylor

      Pages 285-294

   5. Binary Neural Network with Delayed Synapses

      • Tadashi Ae, Yasuhiro Mitsui, Satoshi Fujita, Reiji Aibara

      Pages 295-304

   6. Syntactic Neural Networks in VLSI

      • Simon Lucas, Bob Damper

      Pages 305-314

   7. A New Architectural Approach to Flexible Digital Neural Network Chip Systems

      • Torben Markussen

      Pages 315-324

   8. A VLSI Implementation of a Generic Systolic Synaptic Building Block for Neural Networks

      • Christian Lehmann, François Blayo

      Pages 325-334

   9. A Learning Circuit That Operates by Discrete Means

      • Paul Cockshott, George Milne

      Pages 335-343

   10. A Compact and Fast Silicon Implementation for Layered Neural Nets

       • F. Distante, M. G. Sami, R. Stefanelli, G. Storti-Gajani

       Pages 345-355

3. Arrays for Neural Networks

   1. A Highly Parallel Digital Architecture for Neural Network Emulation

      • Dan Hammerstrom

      Pages 357-366

   2. A Delay-Insensitive Neural Network Engine

      • C. D. Nielsen, J. Staunstrup, S. R. Jones

      Pages 367-376

   3. A VLSI Implementation of Multi-Layered Neural Networks: 2-Performance

      • Bernard Faure, Guy Mazaré

      Pages 377-386

   4. Efficient Implementation of Massive Neural Networks

      • James Austin, Tom Jackson, Alan Wood

      Pages 387-397

   5. Implementing Neural Networks with the Associative String Processor

      • Anargyros Krikelis, Michael Grözinger

      Pages 399-408

This book is an edited selection of the papers presented at the International Workshop on VLSI for Artifidal Intelligence and Neural Networks which was held at the University of Oxford in September 1990. Our thanks go to all the contributors and especially to the programme committee for all their hard work. Thanks are also due to the ACM-SIGARCH, the IEEE Computer Society, and the lEE for publicizing the event and to the University of Oxford and SUNY-Binghamton for their active support. We are particularly grateful to Anna Morris, Maureen Doherty and Laura Duffy for coping with the administrative problems. Jose Delgado-Frias Will Moore April 1991 vii PROLOGUE Artificial intelligence and neural network algorithms/computing have increased in complexity as well as in the number of applications. This in tum has posed a tremendous need for a larger computational power than can be provided by conventional scalar processors which are oriented towards numeric and data manipulations. Due to the artificial intelligence requirements (symbolic manipulation, knowledge representation, non-deterministic computations and dynamic resource allocation) and neural network computing approach (non-programming and learning), a different set of constraints and demands are imposed on the computer architectures for these applications.

• Hardware
• Symbol
• VLSI
• algorithm
• analog
• architecture
• artificial intelligence
• complexity
• computer
• computer architecture
• logic
• network
• neural network
• neural networks
• programming

• State University of New York at Binghamton, Binghamton, USA

  José G. Delgado-Frias

• Oxford University, Oxford, UK

  William R. Moore

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