© 1993

Symbolic Model Checking


Table of contents

  1. Front Matter
    Pages i-xvii
  2. Kenneth L. McMillan
    Pages 1-9
  3. Kenneth L. McMillan
    Pages 11-24
  4. Kenneth L. McMillan
    Pages 25-60
  5. Kenneth L. McMillan
    Pages 61-85
  6. Kenneth L. McMillan
    Pages 87-112
  7. Kenneth L. McMillan
    Pages 113-128
  8. Kenneth L. McMillan
    Pages 129-141
  9. Kenneth L. McMillan
    Pages 143-151
  10. Kenneth L. McMillan
    Pages 153-177
  11. Kenneth L. McMillan
    Pages 179-181
  12. Back Matter
    Pages 183-194

About this book


Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware.
The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention.


VLSI computer design model model checking verification

Authors and affiliations

  1. 1.Carnegie Mellon UniversityAustralia

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