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IDDQ Testing of VLSI Circuits

  • Ravi K. Gulati
  • Charles F. Hawkins

Table of contents

  1. Front Matter
    Pages i-3
  2. Jerry M. Soden, Charles F. Hawkins, Ravi K. Gulati, Weiwei Mao
    Pages 5-17
  3. Roger Perry
    Pages 31-39
  4. Steven D. McEuen
    Pages 41-49
  5. J. A. Segura, V. H. Champac, R. RodríGuez-Montañés, J. Figueras, J. A. Rubio
    Pages 51-62
  6. Weiwei Mao, Ravi K. Gulati
    Pages 63-71
  7. Robert C. Aitken
    Pages 81-89
  8. Sreejit Chakravarty, Minsheng Liu
    Pages 91-99
  9. Josep Rius, J. Figueras
    Pages 101-110
  10. Wojciech Maly, Marek Patyra
    Pages 111-120
  11. Back Matter
    Pages 121-124

About this book

Introduction

Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.

Keywords

CMOS VLSI complexity computer-aided design (CAD) integrated circuit logic metal-oxide-semiconductor transistor simulation stability static-induction transistor

Editors and affiliations

  • Ravi K. Gulati
    • 1
  • Charles F. Hawkins
    • 2
  1. 1.Ford Microelectronics, Inc.USA
  2. 2.University of New MexicoUSA

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