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Table of contents (10 chapters)
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Front Matter
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Introduction
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Front Matter
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TRP For Test Hardware Optimization
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Front Matter
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TRP For Testing Time Minimization
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Front Matter
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TRP For Test Data Volume Reduction
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Front Matter
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Back Matter
Keywords
About this book
Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.
SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.
Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.
Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.
Authors and Affiliations
Bibliographic Information
Book Title: Test Resource Partitioning for System-on-a-Chip
Authors: Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
Series Title: Frontiers in Electronic Testing
DOI: https://doi.org/10.1007/978-1-4615-1113-7
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 2002
Hardcover ISBN: 978-1-4020-7119-5Published: 30 June 2002
Softcover ISBN: 978-1-4613-5400-0Published: 07 November 2012
eBook ISBN: 978-1-4615-1113-7Published: 06 December 2012
Series ISSN: 0929-1296
Edition Number: 1
Number of Pages: XII, 232
Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design
Industry Sectors: Aerospace, Automotive, Electronics, Energy, Utilities & Environment, Engineering, IT & Software, Oil, Gas & Geosciences, Telecommunications