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Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

  • Book
  • © 2014

Overview

Authors:
  1. Ayan Mandal

    1. Computer Science and Engineering, Texas A&M University, College Station, USA

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  2. Sunil P. Khatri

    1. Electrical and Computer Engineering, Texas A&M University, College Station, USA

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  3. Rabi Mahapatra

    1. Computer Science and Engineering, Texas A&M University, College Station, USA

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  • Describes novel methods for high-speed network-on-chip (NoC) design
  • Enables readers to understand NoC design from both circuit and architectural levels
  • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC
  • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art
  • Includes supplementary material: sn.pub/extras

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Table of contents (5 chapters)

  1. Front Matter

    Pages i-xiii
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  2. Introduction

    • Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
    Pages 1-13

  3. Clock Distribution for Fast Networks-on-Chip

    • Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
    Pages 15-66

  4. Fast Network-on-Chip Design

    • Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
    Pages 67-127

  5. Fast On-Chip Data Transfer Using Sinusoid Signals

    • Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
    Pages 129-137

  6. Conclusion and Future Work

    • Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra
    Pages 139-140

  7. Back Matter

    Pages 141-143
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Keywords

About this book

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Authors and Affiliations

  • Computer Science and Engineering, Texas A&M University, College Station, USA

    Ayan Mandal, Rabi Mahapatra

  • Electrical and Computer Engineering, Texas A&M University, College Station, USA

    Sunil P. Khatri

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