Advertisement

Reliability, Availability and Serviceability of Networks-on-Chip

  • Érika Cota
  • Alexandre de Morais Amory
  • Marcelo Soares Lubaszewski

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 1-9
  3. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 11-24
  4. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 25-58
  5. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 59-83
  6. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 85-114
  7. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 115-132
  8. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 133-154
  9. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 155-173
  10. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 175-193
  11. Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 195-200
  12. Back Matter
    Pages 201-209

About this book

Introduction

This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems.  It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.  

This book first presents the characteristics of the NoC design (topologies, structures, routers, wrappers, and protocols), as well as a summary of the terms used in the field and an overview of the existing industrial and academic NoCs. Secondly, the main aspects of the test of a NoC-based system are discussed, starting with the test of the embedded cores where the NoC plays an important role. Current test strategies are presented, such as the reuse of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient reuse of the network, and power-aware and thermal aware NoC-based SoC testing. Then, the challenges and solutions for the NoC infrastructure (interconnects, routers, and network interface) test and diagnosis are presented. Finally, fault tolerance techniques for the NoC are discussed, including techniques based on error control coding, retransmission, fault location, and system reconfiguration.

  • Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems;
  • Includes numerous, current test strategies, including re-use of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware NoC-based SoC testing; 
  • Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

 
 
 
 

 

Keywords

Design for Test Electronics Testing Embedded Systems Fault Tolerance Network on Chip Network-on-Chip Testing On-Chip Communication Architectures Power Aware Test System-on-Chip System-on-Chip Testing Thermal Aware Test

Authors and affiliations

  • Érika Cota
    • 1
  • Alexandre de Morais Amory
    • 2
  • Marcelo Soares Lubaszewski
    • 3
  1. 1.Instituto de InformáticaPorto AlegreBrazil
  2. 2.PUCRS, Faculdade de InformáticaHardware Design Support Group (GAPH)Porto AlegreBrazil
  3. 3.CEITEC SAPorto AlegreBrazil

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4614-0791-1
  • Copyright Information Springer Science+Business Media, LLC 2012
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-0790-4
  • Online ISBN 978-1-4614-0791-1
  • Buy this book on publisher's site
Industry Sectors
Pharma
Automotive
Biotechnology
Electronics
IT & Software
Telecommunications
Energy, Utilities & Environment
Aerospace
Engineering