VLSI Placement and Global Routing Using Simulated Annealing

1. Front Matter

   Pages i-xxvi

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2. Introduction

   • Carl Sechen

   Pages 1-30

3. The Simulated Annealing Algorithm

   • Carl Sechen

   Pages 31-49

4. Placement and Global Routing of Standard Cell Integrated Circuits

   • Carl Sechen

   Pages 51-91

5. Macro/Custom Cell Chip-Planning, Placement, and Global Routing

   • Carl Sechen

   Pages 93-139

6. Average Interconnection Length Estimation

   • Carl Sechen

   Pages 141-179

7. Interconnect-Area Estimation for Macro Cell Placements

   • Carl Sechen

   Pages 181-198

8. An Edge-Based Channel Definition Algorithm for Rectilinear Cells

   • Carl Sechen

   Pages 199-228

9. A Graph-Based Global Router Algorithm

   • Carl Sechen

   Pages 229-246

10. Conclusion

    • Carl Sechen

    Pages 247-253

11. Back Matter

    Pages 255-278

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From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re­ ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in­ terchange algorithm.

• Modulation
• Phase
• Standard
• VLSI
• circuit
• combinatorial optimization
• computer
• computer-aided design (CAD)
• electronics
• gate array
• integrated circuit
• interconnect
• microelectronics
• model
• physics

• Yale University, USA

  Carl Sechen

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