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Analysis of Cache Performance for Operating Systems and Multiprogramming

  • Book
  • © 1989

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Authors:
  1. Anant Agarwal

    1. Massachusetts Institute of Technology, USA

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-xxiii
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  2. Introduction

    • Anant Agarwal
    Pages 1-18

  3. Obtaining Accurate Trace Data

    • Anant Agarwal
    Pages 19-30

  4. Cache Analyses Techniques — An Analytical Cache Model

    • Anant Agarwal
    Pages 31-63

  5. Transient Cache Analysis — Trace Sampling and Trace Stitching

    • Anant Agarwal
    Pages 65-87

  6. Cache Performance Analysis for System References

    • Anant Agarwal
    Pages 89-102

  7. Impact of Multiprogramming on Cache Performance

    • Anant Agarwal
    Pages 103-127

  8. Multiprocessor Cache Analysis

    • Anant Agarwal
    Pages 129-147

  9. Conclusions and Suggestions for Future Work

    • Anant Agarwal
    Pages 149-153

  10. Back Matter

    Pages 155-190
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Keywords

About this book

As we continue to build faster and fast. er computers, their performance is be­ coming increasingly dependent on the memory hierarchy. Both the clock speed of the machine and its throughput per clock depend heavily on the memory hierarchy. The time to complet. e a cache acce88 is oft. en the factor that det. er­ mines the cycle time. The effectiveness of the hierarchy in keeping the average cost of a reference down has a major impact on how close the sustained per­ formance is to the peak performance. Small changes in the performance of the memory hierarchy cause large changes in overall system performance. The strong growth of ruse machines, whose performance is more tightly coupled to the memory hierarchy, has created increasing demand for high performance memory systems. This trend is likely to accelerate: the improvements in main memory performance will be small compared to the improvements in processor performance. This difference will lead to an increasing gap between prOCe880r cycle time and main memory acce. time. This gap must be closed by improving the memory hierarchy. Computer architects have attacked this gap by designing machines with cache sizes an order of magnitude larger than those appearing five years ago. Microproce880r-based RISe systems now have caches that rival the size of those in mainframes and supercomputers.

Authors and Affiliations

  • Massachusetts Institute of Technology, USA

    Anant Agarwal

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