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High Performance Memory Systems

  • Book
  • © 2004

Overview

Editors:
  1. Haldun Hadimioglu

    1. Dept. of Computer and Information Science, Polytechnic University, Brooklyn, USA

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  2. Jeffrey Kuskin

    1. Atheros Communications, Inc., Sunnyvale, USA

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  3. Josep Torrellas

    1. Dept. of Computer Science, University of Illinois, Urbana, USA

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  4. David Kaeli

    1. Dept. of Electrical and Computer Engineering, Northeastern University, Boston, USA

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  5. Ashwini Nanda

    1. IBM TJ Watson Research Ctr., Yorktown Heights, USA

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Table of contents (18 chapters)

  1. Front Matter

    Pages i-xii
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  2. Introduction to High-Performance Memory Systems

    1. Introduction to High-Performance Memory Systems

      • Haldun Hadimioglu, David Kaeli, Jeffrey Kuskin, Ashwini Nanda, Josep Torrellas
      Pages 1-8

  3. Coherence, Synchronization, and Allocation

    1. Front Matter

      Pages 9-9
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    2. Speculative Locks: Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors

      • José F. Martínez, Josep Torrellas
      Pages 11-24

    3. Dynamic Verification of Cache Coherence Protocols

      • Jason F. Cantin, Mikko H. Lipasti, James E. Smith
      Pages 25-42

    4. Timestamp-Based Selective Cache Allocation

      • Martin Karlsson, Erik Hagersten
      Pages 43-59

  4. Power-Aware, Reliable, and Reconfigurable Memory

    1. Front Matter

      Pages 61-61
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    2. Power-Efficient Cache Coherence

      • Craig Saldanha, Mikko H. Lipasti
      Pages 63-78

    3. Improving Power Efficiency with an Asymmetric Set-Associative Cache

      • Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
      Pages 79-96

    4. Memory Issues in Hardware-Supported Software Safety

      • Diana Keen, Frederic T. Chong, Premkumar Devanbu, Matthew Farrens, Jeremy Brown, Jennifer Hollfelder et al.
      Pages 97-112

    5. Reconfigurable Memory Module in the RAMP System for Stream Processing

      • Vason P. Srinii, John Thendean, Jan M. Rabaey
      Pages 113-131

  5. Software-Based Memory Tuning

    1. Front Matter

      Pages 133-133
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    2. Performance of Memory Expansion Technology (MXT)

      • Dan E. Poff, Mohammad Banikazemi, Robert Saccone, Hubertus Franke, Bulent Abali, T. Basil Smith
      Pages 135-152

    3. Profile-Tuned Heap Access

      • Efe Yardimci, David Kaeli
      Pages 153-164

    4. Array Merging: A Technique for Improving Cache and TLB Behavior

      • Daniela Genius, Siddhartha Chatterjee, Alvin R. Lebeck
      Pages 165-179

    5. Software Logging under Speculative Parallelization

      • María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
      Pages 181-195

  6. Architecture-Based Memory Tuning

    1. Front Matter

      Pages 197-197
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    2. An Analysis of Scalar Memory Accesses in Embedded and Multimedia Systems

      • Osman S. Unsal, Zhenlin Wang, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
      Pages 199-212

    3. Bandwidth-Based Prefetching for Constant-Stride Arrays

      • Steven O. Hobbs, John S. Pieper, Stephen C. Root
      Pages 213-225

    4. Performance Potential of Effective Address Prediction of Load Instructions

      • Pritpal S. Ahuja, Joel Emer, Artur Klauser, Shubhendu S. Mukherjee
      Pages 227-246
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Keywords

About this book

The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro­ cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech­ nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte­ grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.

Editors and Affiliations

  • Dept. of Computer and Information Science, Polytechnic University, Brooklyn, USA

    Haldun Hadimioglu

  • Atheros Communications, Inc., Sunnyvale, USA

    Jeffrey Kuskin

  • Dept. of Computer Science, University of Illinois, Urbana, USA

    Josep Torrellas

  • Dept. of Electrical and Computer Engineering, Northeastern University, Boston, USA

    David Kaeli

  • IBM TJ Watson Research Ctr., Yorktown Heights, USA

    Ashwini Nanda

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