Skip to main content
SpringerLink
Log in

Digital VLSI Design with Verilog

A Textbook from Silicon Valley Technical Institute

  • Book
  • © 2008

Overview

Authors:
  1. John Williams

    1. SVTI Inc. Silicon Valley Technical Institute, San Jose CA 95110, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  • Covers the entire verilog language
  • Includes a multiple-lab project in development of a large serialization device
  • Uses simulation examples to teach the writing of code for correct netlist synthesis
  • Shows the use of assertions for the verilog and design-for-test methodology for the hardware

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 119.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (24 chapters)

  1. Front Matter

    Pages I-XXIII
    Download chapter PDF

  2. Week 1 Class 1

    • John Williams
    Pages 1-20

  3. Week 1 Class 2

    • John Williams
    Pages 21-42

  4. Week 2 Class 1

    • John Williams
    Pages 43-60

  5. Week 2 Class 2

    • John Williams
    Pages 61-82

  6. Week 3 Class 1

    • John Williams
    Pages 83-99

  7. Week 3 Class 2

    • John Williams
    Pages 101-112

  8. Week 4 Class 1

    • John Williams
    Pages 113-144

  9. Week 4 Class 2

    • John Williams
    Pages 145-168

  10. Week 5 Class 1

    • John Williams
    Pages 169-184

  11. Week 5 Class 2

    • John Williams
    Pages 185-194

  12. Week 6 Class 1

    • John Williams
    Pages 195-210

  13. Week 6 Class 2

    • John Williams
    Pages 211-230

  14. Week 7 Class 1

    • John Williams
    Pages 231-242

  15. Week 7 Class 2

    • John Williams
    Pages 243-258

  16. Week 8 Class 1

    • John Williams
    Pages 259-277

  17. Week 8 Class 2

    • John Williams
    Pages 279-293

  18. Week 9 Class 1

    • John Williams
    Pages 295-310

  19. Week 9 Class 2

    • John Williams
    Pages 311-335

  20. Week 10 Class 1

    • John Williams
    Pages 337-360
Back to top

Keywords

About this book

Verilog and its usage has come a long way since its original invention in the mid-80s by Phil Moorby. At the time the average design size was around ten thousand gates, and simulation to validate the design was its primary usage. But between then and now designs have increased dramatically in size, and automatic logic synthesis from RTL has become the standard design ?ow for most design. Indeed, the language has evolved and been re-standardized too. Overtheyears,manybookshavebeenwrittenaboutVerilog.Myown,coauthored with Phil Moorby, had the goal of de?ning the language and its usage, providing - amples along the way. It has been updated with ?ve new editions as the language and its usage evolved. However this new book takes a very different and unique view; that of the designer. John Michael Williams has a long history of working and teaching in the ?eld of IC and ASIC design. He brings an indepth presentation of Verilog and how to use it with logic synthesis tools; no other Verilog book has dealt with this topic as deeply as he has. If you need to learn Verilog and get up to speed quickly to use it for synthesis, this book is for you. It is sectioned around a set of lessons including presentation and explanation of new concepts and approaches to design, along with lab sessions.

Authors and Affiliations

  • SVTI Inc. Silicon Valley Technical Institute, San Jose CA 95110, USA

    John Williams

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation