Low-Power Deep Sub-Micron CMOS Logic

1. Front Matter

   Pages i-xiv

   PDF

2. Introduction

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 1-4

3. Power Versus Energy

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 5-9

4. Power Dissipation in Digital CMOS Circuits

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 11-52

5. Reduction of Functional Power Dissipation

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 53-75

6. Reduction of Parasitical Power Dissipation

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 77-91

7. Weak-Inversion Current Reduction

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 93-104

8. Effectiveness of Weak-Inversion Current Reduction

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 105-120

9. Triple-S Circuit Designs

   • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

   Pages 121-138

10. Conclusions

    • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

    Pages 139-140

11. Summary

    • P. R. van der Meer, A. van Staveren, A. H. M. van Roermund

    Pages 141-144

12. Back Matter

    Pages 145-154

    PDF

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in­ dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi­ pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa­ gation delay, which results in a lower data-processing speed performance.

• CMOS
• SECS 841
• Transistor
• integrated circuit
• logic
• van der Meer
• zitter

• Delft University of Technology, Delft, The Netherlands

  P. R. Meer

• National Semiconductor Corporation, Delft, The Netherlands

  A. Staveren

• Eindhoven University of Technology, Eindhoven, The Netherlands

  A. H. M. Roermund

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