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Table of contents

  1. Front Matter
  2. Pages 1-3
  3. Pages 21-42
  4. Pages 43-58
  5. Thomas Grün
    Pages 59-75
  6. Pages 123-140
  7. Pages 141-178
  8. Pages 179-198
  9. Back Matter

About this book

Introduction

This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well-known RISC architecture called DLX are analyzed quantitatively. It is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly.
In an appendix all programs to compute the cost and cycle time of the designs described are listed in C code. Running these simple C programs on a PC is sufficient to verify the results presented. The book addresses design professionals and students in computer architecture.

Keywords

Computerarchitektur Formal Hardware Formaler Hardwareentwurf Hardware Hardware Engineering Hardwareentwicklung Kontrollstruktur architecture complexity computer computer architecture microprocessor performance performance evaluation supercomputer

Bibliographic information

  • DOI https://doi.org/10.1007/3-540-60580-0
  • Copyright Information Springer-Verlag Berlin Heidelberg 1995
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-60580-5
  • Online ISBN 978-3-540-47774-7
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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