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Correct Hardware Design and Verification Methods

11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001 Livingston, Scotland, UK, September 4-7, 2001 Proceedings

  • Conference proceedings
  • © 2001

Overview

Editors:
  1. Tiziana Margaria

    1. Lehrstuhl für Programmiersysteme, Universität Dortmund, Dortmund, Germany

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  2. Tom Melham

    1. Department of Computing Science, University of Glasgow, Glasgow, UK

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2144)

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Table of contents (35 papers)

  1. Hardware Compilation

    1. A Higher-Level Language for Hardware Synthesis

      • Richard Sharp, Alan Mycroft
      Pages 228-243

  2. Tools

    1. Hierarchical Verification Using an MDG-HOL Hybrid Tool

      • Iskander Kort, Sofiene Tahar, Paul Curzon
      Pages 244-258

    2. Exploiting Transition Locality in Automatic Verification

      • Enrico Tronci, Giuseppe Della Penna, Benedetto Intrigila, Marisa Venturini Zilli
      Pages 259-274

    3. Efficient Debugging in a Formal Verification Environment

      • Fady Copty, Amitai Irron, Osnat Weissberg, Nathan Kropp, Gila Kamhi
      Pages 275-292

  3. Model Checking 2

    1. Using Combinatorial Optimization Methods for Quantification Scheduling

      • P. Chauhan, E. Clarke, S. Jha, J. Kukula, H. Veith, D. Wang
      Pages 293-309

    2. Net Reductions for LTL Model-Checking

      • Javier Esparza, Claus Schröter
      Pages 310-324

  4. Component Verification

    1. Formal Verification of the VAMP Floating Point Unit

      • Christoph Berg, Christian Jacobi
      Pages 325-339

    2. A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® Itanium™ Processor Bus Protocol

      • Kanna Shimizu, David L. Dill, Ching-Tsun Chou
      Pages 340-354

    3. The Design and Verification of a Sorter Core

      • Koen Claessen, Mary Sheeran, Satnam Singh
      Pages 355-368

  5. Case Studies

    1. Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip

      • Xiaohua Kong, Radu Negulescu, Larry Weidong Ying
      Pages 370-385

    2. Using Abstract Specifications to Verify PowerPC™ Custom Memories by Symbolic Trajectory Evaluation

      • Jayanta Bhadra, Andrew Martin, Jacob Abraham, Magdy Abadir
      Pages 386-402

  6. Algorithm Verification

    1. Formal Verification of Conflict Detection Algorithms

      • Ricky Butler, Víctor Carreño, Gilles Dowek, César Muñoz
      Pages 403-417

    2. Induction-Oriented Formal Verification in Symmetric Interconnection Networks

      • Eric Gascard, Laurence Pierre
      Pages 418-432

    3. A Framework for Microprocessor Correctness Statements

      • Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones
      Pages 433-448

  7. Duration Calculus

    1. From Operational Semantics to Denotational Semantics for Verilog

      • Zhu Huibiao, Jonathan P. Bowen, He Jifeng
      Pages 449-464

    2. Efficient Verification of a Class of Linear Hybrid Automata Using Linear Programming

      • Li Xuandong, Pei Yu, Zhao Jianhua, Li Yong, Zheng Tao, Zheng Guoliang
      Pages 465-479

  8. Back Matter

    Pages 481-481
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Keywords

About this book

This volume contains the proceedings of CHARME 2001, the Eleventh Advanced Research Working Conference on Correct Hardware Design and Veri?cation Methods. CHARME 2001 is the 11th in a series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and hardware-like systems. Previous events in the ‘CHARME’ series were held in Bad Herrenalb (1999), Montreal (1997), Frankfurt (1995), Arles (1993), and Torino (1991). This series of meetings has been organized in cooperation with IFIP WG 10.5 and WG 10.2. Prior meetings, stretching backto the earliest days of formal hardware veri?cation, were held under various names in Miami (1990), Leuven (1989), Glasgow (1988), Grenoble (1986), Edinburgh (1985), and Darmstadt (1984). The convention is now well-established whereby the European CHARME conference alternates with its biennial counterpart, the International Conference on Formal Methods in Computer-Aided Design (FMCAD), which is held on even-numbered years in the USA. The conference tookplace during 4–7 September 2001 at the Institute for System Level Integration in Livingston, Scotland. It was co-hosted by the - stitute and the Department of Computing Science of Glasgow University and co-sponsored by the IFIP TC10/WG10.5 Working Group on Design and En- neering of Electronic Systems. CHARME 2001 also included a scienti?c session and social program held jointly with the 14th International Conference on Th- rem Proving in Higher Order Logics (TPHOLs), which was co-located in nearby Edinburgh.

Editors and Affiliations

  • Lehrstuhl für Programmiersysteme, Universität Dortmund, Dortmund, Germany

    Tiziana Margaria

  • Department of Computing Science, University of Glasgow, Glasgow, UK

    Tom Melham

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