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  • Conference proceedings
  • © 2001

Field-Programmable Logic and Applications

11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2147)

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Table of contents (74 papers)

  1. Runtime Recon.guration 1

    1. Configuration Caching and Swapping

      • Suraj Sudhir, Suman Nath, Seth Copen Goldstein
      Pages 192-202
  2. Graphics and Vision

    1. Multiple Stereo Matching Using an Extended Architecture

      • Miguel Arias-Estrada, Juan M. Xicotencatl
      Pages 203-212
    2. Implementation of a NURBS to Bézier Conversor with Constant Latency

      • Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
      Pages 213-222
    3. Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems

      • Sergio A. Cuenca, Francisco Ibarra, Rafael Alvarez
      Pages 223-231
  3. Invited Keynote 2

  4. Place and Route 2

    1. Tightly Integrated Placement and Routing for FPGAs

      • Parivallal Kannan, Dinesh Bhatia
      Pages 233-242
  5. Networking

    1. Reconfigurable Router Modules Using Network Protocol Wrappers

      • Florian Braun, John Lockwood, Marcel Waldvogel
      Pages 254-263
    2. Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware

      • Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
      Pages 264-274
  6. Processor Interaction

    1. The MOLEN ρμ-Coded Processor

      • Stamatis Vassiliadis, Stephan Wong, Sorin Cotöfană
      Pages 275-285
    2. Run-Time Optimized Reconfiguration Using Instruction Forecasting

      • Marios Iliopoulos, Theodore Antonakopoulos
      Pages 286-295
    3. CRISP: A Template for Reconfigurable Instruction Set Processors

      • Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins
      Pages 296-305
  7. Applications

    1. Evaluation of an FPGA Implementation of the Discrete Element Method

      • Benjamin Carrion Schafer, Steven F. Quigley, Andrew H. C. Chan
      Pages 306-314
    2. Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers

      • Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam
      Pages 315-325
    3. A Reconfigurable Embedded Input Device for Kinetically Challenged Persons

      • Apostolos Dollas, Kyprianos Papademetriou, Nikolaos Aslanides, Tom Kean
      Pages 326-335
  8. Methodology 1

    1. Bubble Partitioning for LUT-Based Sequential Circuits

      • Frank Wolz, Reiner Kolla
      Pages 336-345
    2. Placing, Routing, and Editing Virtual FPGAs

      • Löic Lagadec, Dominique Lavenier, Erwan Fabiani, Bernard Pottier
      Pages 357-366
  9. DSP 2

    1. A Music Synthesizer on FPGA

      • Takashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo Hirano
      Pages 377-387

Editors and Affiliations

  • Division of Informatics, University of Edinburgh, Edinburgh, UK

    Gordon Brebner

  • School of Electrical and Electronic Engineering, Queen’s University of Belfast, Belfast, UK

    Roger Woods

Bibliographic Information

Buy it now

Buying options

eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access