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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings

  • Jorge Juan Chico
  • Enrico Macii
Conference proceedings PATMOS 2003

Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Table of contents

  1. Low Power Issues in Processors and Multimedia

    1. Massimo Ravasi, Marco Mattavelli, Paul Schumacher, Robert Turney
      Pages 440-450
  2. Poster Session 1

    1. X. Michel, A. Verle, N. Azémard, P. Maurine, D. Auvergne
      Pages 451-460
    2. G. Tosik, F. Gaffiot, Z. Lisik, I. O’Connor, F. Tissafi-Drissi
      Pages 461-470
    3. B. Javadi, M. Naderi, H. Pedram, A. Afzali-Kusha, M. K. Akbari
      Pages 471-480
    4. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
      Pages 491-500
    5. D. Guerrero, G. Wilke, J. L. Güntzel, M. J. Bellido, J. Juan Chico, P. Ruiz-de-Clavijo et al.
      Pages 501-510
  3. Poster Session 2

    1. Dongsheng Wang, Peter Suaris, Nan-chi Chou
      Pages 511-519
    2. Byung-Soo Choi, Dong-Ik Lee
      Pages 520-529
    3. Andrea Acquaviva, Alessandro Bogliolo
      Pages 540-549
    4. Wen-Tsong Shiue, Weetit Wanalertlak
      Pages 550-558
  4. Poster Session 3

    1. Anatoly Prihozhy, Marco Mattavelli, Daniel Mlynek
      Pages 569-579
    2. Javier Resano, Daniel Mozos, Elena Pérez, Hortensia Mecha, Julio Septién
      Pages 580-589
    3. Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
      Pages 599-606
    4. K. Tatas, K. Siozios, N. Vasiliadis, D. J. Soudris, S. Nikolaidis, S. Siskos et al.
      Pages 607-616
    5. María C. Molina, Rafael Ruiz Sautua, José M. Mendías, Román Hermida
      Pages 617-627
  5. Back Matter

About these proceedings

Introduction

Welcome to the proceedings of PATMOS 2003. This was the 13th in a series of international workshops held in several locations in Europe. Over the years, PATMOS has gained recognition as one of the major European events devoted to power and timing aspects of integrated circuit and system design. Despite its signi?cant growth and development, PATMOS can still be considered as a very informal forum, featuring high-level scienti?c presentations together with open discussions and panel sessions in a free and relaxed environment. This year, PATMOS took place in Turin, Italy, organized by the Politecnico di Torino, with technical co-sponsorship from the IEEE Circuits and Systems Society and the generous support of the European Commission, as well as that of several industrial sponsors, including BullDAST, Cadence, Mentor Graphics, STMicroelectronics, and Synopsys. The objective of the PATMOS workshop is to provide a forum to discuss and investigate the emerging problems in methodologies and tools for the design of new generations of integrated circuits and systems. A major emphasis of the technical program is on speed and low-power aspects, with particular regard to modeling, characterization, design, and architectures.

Keywords

CAD design methods CAD tools CMOS Circuit design Flüssigkristallbildschirm IC technology Multimedia Performance Scheduling architecture computer architecture low power design low voltage memory performance analysis processor

Editors and affiliations

  • Jorge Juan Chico
    • 1
  • Enrico Macii
    • 2
  1. 1.Departamento de Tecnología ElectrónicaUniversidad de Sevilla Sevilla(Spain)
  2. 2.Politecnico di TorinoTorinoItaly

Bibliographic information

  • DOI https://doi.org/10.1007/b12033
  • Copyright Information Springer-Verlag Berlin Heidelberg 2003
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-20074-1
  • Online ISBN 978-3-540-39762-5
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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