Skip to main content
SpringerLink
Log in
Book cover

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings

  • Conference proceedings
  • © 2003

Overview

Editors:
  1. Jorge Juan Chico

    1. Departamento de Tecnología Electrónica, Universidad de Sevilla Sevilla, (Spain)

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. Enrico Macii

    1. Politecnico di Torino, Torino, Italy

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2799)

Included in the following conference series:

Conference proceedings info: PATMOS 2003.

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (68 papers)

  1. Asynchronous Techniques

    1. Static Implementation of QDI Asynchronous Primitives

      • P. Maurine, J. B. Rigaud, F. Bouesse, G. Sicard, M. Renaudin
      Pages 181-191

  4. RTL Power Modeling and Memory Optimisation

    1. Statistical Power Estimation of Behavioral Descriptions

      • B. Arts, A. Bellu, L. Benini, N. van der Eng, M. Heijligers, E. Macii et al.
      Pages 197-207

    2. A Statistical Power Model for Non-synthetic RTL Operators

      • Maurizio Bruno, Alberto Macii, Massimo Poncino
      Pages 208-218

    3. Energy Efficient Register Renaming

      • Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
      Pages 219-228

    4. Stand-by Power Reduction for Storage Circuits

      • S. Cserveny, J. -M. Masgonty, C. Piguet
      Pages 229-238

    5. A Unified Framework for Power-Aware Design of Embedded Systems

      • José L. Ayala, Marisa López-Vallejo
      Pages 239-248

  5. High-Level Modeling

    1. A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems

      • Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
      Pages 249-258

    2. High-Level Area and Current Estimation

      • Fei Li, Lei He, Joe Basile, Rakesh J. Patel, Hema Ramamurthy
      Pages 259-268

    3. Switching Activity Estimation in Non-linear Architectures

      • Alberto García-Ortiz, Lukusa Kabulepa, Manfred Glesner
      Pages 269-278

    4. Instruction Level Energy Modeling for Pipelined Processors

      • S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas
      Pages 279-288

    5. Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level

      • Marc Leeman, David Atienza, Francky Catthoor, V. De Florio, G. Deconinck, J. M. Mendias et al.
      Pages 289-298

  6. Power Efficient Technologies and Designs

    1. An Adiabatic Charge Pump Based Charge Recycling Design Style

      • Vineela Manne, Akhilesh Tyagi
      Pages 299-308

    2. Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing

      • Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel
      Pages 309-318

    3. Low-Power Response Time Accelerator with Full Resolution for LCD Panel

      • Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
      Pages 319-327

    4. Memory Compaction and Power Optimization for Wavelet-Based Coders

      • V. Ferentinos, M. Milia, G. Lafruit, J. Bormans, F. Catthoor
      Pages 328-337
Back to top

Other volumes

  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Keywords

About this book

Welcome to the proceedings of PATMOS 2003. This was the 13th in a series of international workshops held in several locations in Europe. Over the years, PATMOS has gained recognition as one of the major European events devoted to power and timing aspects of integrated circuit and system design. Despite its signi?cant growth and development, PATMOS can still be considered as a very informal forum, featuring high-level scienti?c presentations together with open discussions and panel sessions in a free and relaxed environment. This year, PATMOS took place in Turin, Italy, organized by the Politecnico di Torino, with technical co-sponsorship from the IEEE Circuits and Systems Society and the generous support of the European Commission, as well as that of several industrial sponsors, including BullDAST, Cadence, Mentor Graphics, STMicroelectronics, and Synopsys. The objective of the PATMOS workshop is to provide a forum to discuss and investigate the emerging problems in methodologies and tools for the design of new generations of integrated circuits and systems. A major emphasis of the technical program is on speed and low-power aspects, with particular regard to modeling, characterization, design, and architectures.

Editors and Affiliations

  • Departamento de Tecnología Electrónica, Universidad de Sevilla Sevilla, (Spain)

    Jorge Juan Chico

  • Politecnico di Torino, Torino, Italy

    Enrico Macii

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation