Logic Synthesis and Verification Algorithms

  • Gary D. Hachtel
  • Fabio Somenzi

Table of contents

  1. Front Matter
    Pages i-xxxii
  2. Introduction

  3. Two Level Logic Synthesis

  4. Models of Sequential Systems

  5. Multilevel Logic Synthesis

  6. Back Matter
    Pages 523-564

About this book


Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.


Automat Boolean algebra VLSI algorithms automata formal verification logic verification

Authors and affiliations

  • Gary D. Hachtel
    • 1
  • Fabio Somenzi
    • 1
  1. 1.University of ColoradoUSA

Bibliographic information

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