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CMOS PLL Synthesizers: Analysis and Design

  • Authors
  • Keliu Shu
  • Edgar Sánchez-Sinencio

Part of the The International Series in Engineering and Computer Science book series (SECS, volume 783)

Table of contents

About this book

Introduction

CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer.

This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.

Keywords

CMOS PLL Phase filter fractional-N synthesizer loop capacitance multiplier phase-switching prescaler sigma-delta modulator

Bibliographic information

  • DOI https://doi.org/10.1007/b102174
  • Copyright Information Springer Science+Business Media, Inc. 2005
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-0-387-23668-1
  • Online ISBN 978-0-387-23669-8
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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