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© 2020

Design and Testing of Reversible Logic

  • Ashutosh Kumar Singh
  • Masahiro Fujita
  • Anand Mohan
  • Covers the current research under design, synthesis, and testing on a single platform

  • Discusses numerous step-by-step methodologies for each stream

  • Provides applications of reversible logic to emerging technologies

Book

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 577)

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Fundamental Concepts

    1. Front Matter
      Pages 1-1
    2. H. M. Gaur, T. N. Sasamal, A. K. Singh, A. Mohan, D. K. Pradhan
      Pages 3-18
  3. Design & Synthesis

    1. Front Matter
      Pages 19-19
    2. I. Gassoumi, L. Touil, B. Ouni
      Pages 21-35
    3. T. N. Sasamal, H. M. Gaur, A. K. Singh, A. Mohan
      Pages 37-48
    4. C. Bandyopadhyay, S. Parekh, D. Roy, H. Rahaman
      Pages 49-64
    5. T. N. Sasamal, H. M. Gaur, A. K. Singh, A. Mohan
      Pages 115-128
  4. Test Approaches

    1. Front Matter
      Pages 129-129
    2. H. M. Gaur, T. N. Sasamal, A. K. Singh, A. Mohan
      Pages 153-167
    3. B. Mondal, C. Bandyopadhyay, A. Bhattacharjee, H. Rahaman
      Pages 169-184
  5. Applications to Emerging Technologies

    1. Front Matter
      Pages 213-213
    2. A. Bhattacharjee, C. Bandyopadhyay, B. Mondal, Robert Wille, Rolf Drechsler, H. Rahaman
      Pages 215-231
    3. A. Kamaraj, P. Marichamy, J. Senthil Kumar, S. Selva Nidhyananthan, C. Kalyana Sundaram
      Pages 233-250
  6. Back Matter
    Pages 263-265

About this book

Introduction

The book compiles efficient design and test methodologies for the implementation of reversible logic circuits. The methodologies covered in the book are design approaches, test approaches, fault tolerance in reversible circuits and physical implementation techniques. The book also covers the challenges and the reversible logic circuits to meet these challenges stimulated during each stage of work cycle. The novel computing paradigms are being explored to serve as a basis for fast and low power computation.

Keywords

Reversible Logic Circuits Design & Automation Design for Testability Fault Tolerance Computing Emerging Technologies Quantum Computation Reversible Logic Testing Fault Detection Logic Circuit Optimization Probabilistic Synthesis Approaches

Editors and affiliations

  • Ashutosh Kumar Singh
    • 1
  • Masahiro Fujita
    • 2
  • Anand Mohan
    • 3
  1. 1.Department of Computer ApplicationsNational Institute of TechnologyKurukshetraIndia
  2. 2.VLSI Design and Education CenterUniversity of TokyoTokyoJapan
  3. 3.Department of Electronics EngineeringIndian Institute of TechnologyVaranasiIndia

About the editors

Ashutosh Kumar Singh is an esteemed researcher and academician in the domain of Electrical and Computer Engineering. Currently, he is working as a Professor and Head, Department of Computer Applications, National Institute of Technology, Kurukshetra, India. He has more than 19 years research, teaching and administrative experience in various University systems of the India, UK, Australia and Malaysia. Dr. Singh obtained his Ph.D. degree in Electronics Engineering from Indian Institute of Technology-BHU, India; Post Doc from Department of Computer Science, University of Bristol, United Kingdom and Charted Engineer from United Kingdom. His research area includes Verification, Synthesis, Design and Testing of Digital Circuits, Predictive Data Analytics, Data Security in Cloud, Web Technology. He has published more than 180 research papers till now in peer-reviewed journals, conferences and news magazines and in these areas. He has also co-authored seven books including “Web Spam Detection Application using Neural Network”, “Digital Systems Fundamentals” and “Computer System Organization & Architecture”. He has worked as principal investigator/investigator for six sponsored research projects and was a key member on a project from EPSRC (United Kingdom) entitled “Logic Verification and Synthesis in New Framework”. Dr. Singh has visited several countries including Australia, United Kingdom, South Korea, China, Thailand, Indonesia, Japan and USA for collaborative research work, invited talks and to present his research work. He had been entitled for 13 awards such as Merit Awards-2003 (Institute of Engineers), Best Poster Presenter-99 in 86th Indian Science Congress held in Chennai, India, Best Paper Presenter of NSC’99 INDIA and Bintulu Development Authority Best Postgraduate Research Paper Award for 2010, 2011, 2012. He has served as an Editorial Board Member of International Journal of Networks and Mobile Technologies, International Journal of Digital Content Technology and its Applications. Also he has shared his experience as a Guest Editor for Pertanika Journal of Science and Technology, Chairman of CUTSE International Conference 2011, Conference Chair of series of International Conference on Smart Computing and Communication (ICSCC), and as editorial board member of UNITAR e-journal. He is involved in reviewing process in different journals and conferences of repute including IEEE transaction of computer, IET, IEEE conference on ITC, ADCOM, etc.

Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs having more than several million gates. The developed tool has been used in production internally at Fujitsu and externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has been involved in a Japanese governmental research project for dependable system designs and has developed a formal verifier for C programs that could be used for both hardware and embedded software designs. The tool is now under evaluation jointly with industry under governmental support. He has authored and co-authored 10 books, and has more than 200 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of web-based programs and embedded programs.

Anand Mohan, former Director of National Institute of Technology (NIT), Kurukshetra, Haryana has 41 years of rich experience in teaching, research, industrial R & D. He is currently working as Professor (HAG) in the Department of Electronics Engineering, IIT(BHU), Varanasi. He has made notable research contributions in the areas of robust watermarking, telemedicine, and fault tolerant digital system design. Eleven students have been awarded Ph.D. degree under his supervision. Prof. Mohan has successfully completed eight sponsored projects funded by MHRD, AICTE and Ministry of Communication & Information Technology, Govt. of India, New Delhi. He has published 145 research papers in reputed international/national journals and conference proceedings. Prof. Mohan has provided national level leadership to the defence-related R & D activities as Chairman of Armament Sensors & Electronics (ASE) Panel under ARMREB, DRDO, Ministry of Defence, Govt. of India. He has been associated with several important academic and research advisory committees as Chairman of Ad-hoc committees of Software Technology Parks of India (STPI), DRDO laboratories, NAAC, and AICTE and Member of DST, UGC, and CSIR committees. He obtained UG, PG and Ph.D. degrees in Electronics Engineering from Banaras Hindu University. He is recipient of ‘Life Time Achievement Award’ conferred by Kamla Nehru Institute of Technology (KNIT), Sultanpur (2016). He is Fellow of Institution of Electronics and Telecommunication Engineers (IETE), Fellow of Institution of Engineers (I), Member, IEEE, USA life member of Project Management Associates (PMA), New Delhi, and Life member of Indian Society of Technical Education (ISTE), New Delhi.

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