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Test Generation of Crosstalk Delay Faults in VLSI Circuits

  • S. Jayanthy
  • M.C. Bhuvaneswari

Table of contents

  1. Front Matter
    Pages i-xi
  2. S. Jayanthy, M. C. Bhuvaneswari
    Pages 1-14
  3. S. Jayanthy, M. C. Bhuvaneswari
    Pages 15-35
  4. S. Jayanthy, M. C. Bhuvaneswari
    Pages 37-55
  5. S. Jayanthy, M. C. Bhuvaneswari
    Pages 109-123
  6. S. Jayanthy, M. C. Bhuvaneswari
    Pages 151-156

About this book

Introduction

This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

Keywords

Crosstalk delay faults Very Large Scale Integration Deterministic Algorithms Genetic Algorithm Fuzzy Delay Model

Authors and affiliations

  • S. Jayanthy
    • 1
  • M.C. Bhuvaneswari
    • 2
  1. 1.Department of Electronics and Communication EngineeringSri Ramakrishna Engineering CollegeCoimbatoreIndia
  2. 2.Department of Electrical and Electronics EngineeringPSG College of TechnologyCoimbatoreIndia

Bibliographic information

  • DOI https://doi.org/10.1007/978-981-13-2493-2
  • Copyright Information Springer Science+Business Media Singapore 2019
  • Publisher Name Springer, Singapore
  • eBook Packages Engineering
  • Print ISBN 978-981-13-2492-5
  • Online ISBN 978-981-13-2493-2
  • Buy this book on publisher's site
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