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Table of contents

  1. Front Matter
    Pages i-xxi
  2. Vaibbhav Taraate
    Pages 1-16
  3. Vaibbhav Taraate
    Pages 17-24
  4. Vaibbhav Taraate
    Pages 25-50
  5. Vaibbhav Taraate
    Pages 51-62
  6. Vaibbhav Taraate
    Pages 63-95
  7. Vaibbhav Taraate
    Pages 97-117
  8. Vaibbhav Taraate
    Pages 119-139
  9. Vaibbhav Taraate
    Pages 141-158
  10. Vaibbhav Taraate
    Pages 159-172
  11. Vaibbhav Taraate
    Pages 173-196
  12. Vaibbhav Taraate
    Pages 197-210
  13. Vaibbhav Taraate
    Pages 211-230
  14. Vaibbhav Taraate
    Pages 231-245
  15. Vaibbhav Taraate
    Pages 247-262
  16. Vaibbhav Taraate
    Pages 263-276
  17. Vaibbhav Taraate
    Pages 277-290
  18. Back Matter
    Pages 291-307

About this book

Introduction

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

Keywords

FPGA SOC System Level Verification ASIC Prototyping STA scripts SOC Synthesis

Authors and affiliations

  • Vaibbhav Taraate
    • 1
  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

Bibliographic information

  • DOI https://doi.org/10.1007/978-981-10-8776-9
  • Copyright Information Springer Nature Singapore Pte Ltd. 2019
  • Publisher Name Springer, Singapore
  • eBook Packages Engineering
  • Print ISBN 978-981-10-8775-2
  • Online ISBN 978-981-10-8776-9
  • Buy this book on publisher's site
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