Adiabatic Logic

Future Trend and System Level Perspective

  • Philip Teichmann

Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 34)

Table of contents

  1. Front Matter
    Pages I-XVII
  2. Philip Teichmann
    Pages 1-3
  3. Philip Teichmann
    Pages 5-22
  4. Philip Teichmann
    Pages 23-63
  5. Philip Teichmann
    Pages 65-81
  6. Philip Teichmann
    Pages 83-111
  7. Philip Teichmann
    Pages 113-143
  8. Philip Teichmann
    Pages 145-154
  9. Philip Teichmann
    Pages 155-158
  10. Back Matter
    Pages 159-166

About this book


Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.


Adiabatic Circuits CMOS Design Circuits & Systems Clock Frequency Devices Energy Efficient Microelectronics Low-Power Electronics Microelectronics Oscillators

Authors and affiliations

  • Philip Teichmann
    • 1
  1. 1.Lehrstuhl für Technische ElektronikTechnische Universität MünchenMunichGermany

Bibliographic information

  • DOI
  • Copyright Information Springer Science+Business Media B.V. 2012
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering Engineering (R0)
  • Print ISBN 978-94-007-2344-3
  • Online ISBN 978-94-007-2345-0
  • Series Print ISSN 1437-0387
  • Buy this book on publisher's site
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