Pipelined ADC Design and Enhancement Techniques

  • Imran Ahmed

Part of the Analog Circuits and Signal Processing book series (ACSP)

Table of contents

  1. Front Matter
    Pages i-xxv
  2. Pipelined ADC Design

    1. Front Matter
      Pages 6-6
    2. Imran Ahmed
      Pages 1-4
    3. Imran Ahmed
      Pages 7-17
    4. Imran Ahmed
      Pages 19-38
    5. Imran Ahmed
      Pages 49-61
  3. Pipelined ADC Enhancement Techniques

    1. Front Matter
      Pages 64-64
    2. Imran Ahmed
      Pages 201-202
  4. Back Matter
    Pages 203-211

About this book


Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs. Written for both researchers and professionals, Pipelined ADC Design and Enhancement Techniques provides:

i.) A tutorial discussion, for those new to pipelined ADCs, of the basic design and tradeoffs involved in designing a pipelined ADC

ii.) A detailed discussion of four novel silicon tested pipelined ADC topologies geared towards those looking to gain insight into state-of-the-art design in the area. The ADCs detailed include:

- An 11-bit 45MS/s ADC which rapidly digitally calibrates in the background both DAC and gain errors

- A 10-bit ADC with power scalable between 50MS/s (35mW) to 1kS/s (15µW)

- A 10-bit ADC for use in sub-sampled systems with a technique to eliminate the front-end sample-and-hold

- A 10-bit, 50MS/s ADC which uses a capacitive charge pump based approach to enable a very small power consumption of 9.9mW.


Data Converters Digital Circuit Design Low Power Design analog circuit design calibration circuit design electronics pipelined ADC reconfigurable testing

Authors and affiliations

  • Imran Ahmed
    • 1
  1. 1.Kapik IntegrationTorontoCanada

Bibliographic information

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