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VLSI Chip Design with the Hardware Description Language VERILOG

An Introduction Based on a Large RISC Processor Design

  • Ulrich Golze

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Introduction

    1. Ulrich Golze
      Pages 1-7
  3. Design of VLSI Circuits

    1. Ulrich Golze
      Pages 9-23
  4. RISC Architectures

    1. Ulrich Golze
      Pages 25-37
  5. Short Introduction to VERILOG

    1. Ulrich Golze
      Pages 39-46
  6. External Specification of Behavior

    1. Ulrich Golze
      Pages 47-71
  7. Internal Specification of Coarse Structure

    1. Ulrich Golze
      Pages 73-112
  8. Pipeline of the Coarse Structure Model

    1. Ulrich Golze
      Pages 113-161
  9. Synthesis of Gate Model

    1. Ulrich Golze
      Pages 163-203
  10. Testing, Testability, Tester, and Testboard

    1. Ulrich Golze
      Pages 205-245
  11. Summary and Prospect

    1. Ulrich Golze
      Pages 247-255
  12. HDL Models for Circuits and Architectures

    1. Front Matter
      Pages 259-259
    2. Ulrich Golze
      Pages 261-346
  13. Back Matter
    Pages 347-360

About this book

Introduction

This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.

Keywords

Hardware-Beschreibungssprachen Hardwarebeschreibungssprache LSI Mikroprozessoren RISC architectures RISC-Architekturen VLSI Verilog circuit circuit design hardware hardware description languages microprocessor programming programming language

Authors and affiliations

  • Ulrich Golze
    • 1
  1. 1.Department of Integrated Circuit Design (E.I.S.)Technical University of BraunschweigBraunschweigGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-642-61001-1
  • Copyright Information Springer-Verlag Berlin Heidelberg 1996
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-642-64650-8
  • Online ISBN 978-3-642-61001-1
  • Buy this book on publisher's site
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