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Processor Architecture

From Dataflow to Superscalar and Beyond

  • Jurij Šilc
  • Borut Robič
  • Theo Ungerer

Table of contents

  1. Front Matter
    Pages I-XXII
  2. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 1-54
  3. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 55-97
  4. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 99-122
  5. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 123-219
  6. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 221-245
  7. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 247-298
  8. Jurij Šilc, Borut Robič, Theo Ungerer
    Pages 299-333
  9. Back Matter
    Pages 335-391

About this book

Introduction

This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It starts with a review of past techniques, continues with a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and implementations in sample processors, and ends with a thorough review of the research techniques that will lead to future microprocessors.

Keywords

Control Speculation EPIC Mikroprozessoren Paralleles Rechnen Processor architecture Prozessor-Architektur Scheduling Verteilte Systeme computer organization microprocessors parallel processing processor

Authors and affiliations

  • Jurij Šilc
    • 1
  • Borut Robič
    • 2
  • Theo Ungerer
    • 3
  1. 1.Computer Systems DepartmentJožef Stefan InstituteLjubljanaSlovenia
  2. 2.Faculty of Computer and Information ScienceUniversity of LjubljanaLjubljanaSlovenia
  3. 3.Department of Computer Design and Fault ToleranceUniversity of KarsruheKarlsruheGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-642-58589-0
  • Copyright Information Springer-Verlag Berlin Heidelberg 1999
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-64798-0
  • Online ISBN 978-3-642-58589-0
  • Buy this book on publisher's site
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