Transactions on High-Performance Embedded Architectures and Compilers III

  • Per Stenström

Part of the Lecture Notes in Computer Science book series (LNCS, volume 6590)

Table of contents

  1. Front Matter
  2. Third International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)

    1. Front Matter
      Pages 1-1
    2. Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero
      Pages 3-23
    3. Chun-Chieh Lin, Chuen-Liang Chen
      Pages 24-42
    4. Subhradyuti Sarkar, Dean M. Tullsen
      Pages 43-68
    5. Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous
      Pages 69-88
  3. Eighth MEDEA Workshop (Selected Papers)

    1. Front Matter
      Pages 89-89
    2. Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonia Prete
      Pages 91-92
    3. Matthias Blumrich, Valentina Salapura, Alan Gara
      Pages 93-114
    4. Fernando Latorre, Grigorios Magklis, Jose González, Pedro Chaparro, Antonio González
      Pages 115-134
    5. Isao Kotera, Kenta Abe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
      Pages 135-153
    6. Jan Hoogerbrugge, Andrei Terechko
      Pages 154-173
  4. Regular Papers

    1. Front Matter
      Pages 175-175
    2. Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Samir Bouaziz
      Pages 177-200
    3. Harald Devos, Jan Van Campenhout, Ingrid Verbauwhede, Dirk Stroobandt
      Pages 201-216
  5. First Workshop on Programmability Issues for Multi-core Computers (MULTIPROG)

    1. Front Matter
      Pages 217-217
    2. Tobias Klug, Michael Ott, Josef Weidendorfer, Carsten Trinitis
      Pages 219-235
    3. Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham, Ian Watson
      Pages 236-255
  6. Back Matter

About this book


Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section  contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.


application specific systems dynamic cache partitioning dynamic compilation embedded computing embedded systems high performance computing memory hierarchies memory systems multicore systems parallelization power-aware systems design processor architectures program analysis program optimization reconfigurable architectures supercomputing transactional memory virtual machine

Editors and affiliations

  • Per Stenström
    • 1
  1. 1.Department of Computer Science and EngineeringChalmers University of TechnologyGothenburgSweden

Bibliographic information