Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers

  • Lars Svensson
  • José Monteiro
Conference proceedings PATMOS 2008

Part of the Lecture Notes in Computer Science book series (LNCS, volume 5349)

Table of contents

  1. Front Matter
  2. Session 1: Low-Leakage and Subthreshold Circuits

    1. Biswajit Mishra, Bashir M. Al-Hashimi
      Pages 1-10
    2. Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
      Pages 21-30
    3. Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
      Pages 31-41
  3. Session 2: Low-Power Methods and Models

    1. Ashoka Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
      Pages 42-51
    2. Roni Wiener, Gila Kamhi, Moshe Y. Vardi
      Pages 52-61
    3. Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
      Pages 62-71
    4. Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed
      Pages 72-81
    5. Vasily G. Moshnyaga
      Pages 82-92
  4. Session 3: Arithmetic and Memories

    1. Ioannis Kouretas, Vassilis Paliouras
      Pages 93-102
    2. Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki
      Pages 103-115
    3. Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel
      Pages 116-125
    4. Yan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel
      Pages 126-135
  5. Session 4: Variability and Statistical Timing

    1. Massimo Alioto, Gaetano Palumbo, Melita Pennisi
      Pages 136-145
    2. Monica Figueiredo, Rui L. Aguiar
      Pages 146-155
    3. Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
      Pages 156-166
    4. Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann
      Pages 167-177
    5. Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah
      Pages 178-187
  6. Session 5: Synchronization and Interconnect

    1. Francisco Fernández-Nogueira, Josep Carmona
      Pages 188-198
    2. Rostislav (Reuven) Dobkin, Ran Ginosar
      Pages 199-208
    3. Alberto García-Ortiz, Leandro S. Indrusiak, Tudor Murgan, Manfred Glesner
      Pages 219-228
  7. Session 6: Power Supplies and Switching Noise

    1. Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres
      Pages 229-236
    2. Giorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco
      Pages 237-246
    3. Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, L. Miguel Silveira
      Pages 247-257
    4. Nuno Dias, Marcelino Santos, Floriberto Lima, Beatriz Borges, Júlio Paisana
      Pages 258-267
  8. Session 7: Low-Power Circuits; Reconfigurable Architectures

    1. Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija
      Pages 268-276
    2. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
      Pages 277-286
    3. Maurice Keller, William Marnane
      Pages 287-296
    4. Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
      Pages 297-306
    5. Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
      Pages 307-317
  9. Poster Session 1: Circuits and Methods

    1. Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
      Pages 318-327
    2. Omid Mirmotahari, Yngvar Berg
      Pages 328-337
    3. Marco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti
      Pages 338-347
    4. Martin Simlastik, Viera Stopjakova
      Pages 348-358
    5. Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien
      Pages 359-368
  10. Poster Session 2: Power and Delay Modeling

    1. Ruzica Jevtic, Carlos Carreras
      Pages 369-378
    2. Gustavo Callou, Paulo Maciel, Ermeson Carneiro, Bruno Nogueira, Eduardo Tavares, Meuse Oliveira Jr.
      Pages 379-388
    3. Alejandro Millan, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo
      Pages 389-398
    4. Francesc Moll, Joan Figueras, Antonio Rubio
      Pages 409-418
  11. Special Session: Power Optimizations Addressing Reconfigurable Architectures

    1. Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker
      Pages 419-428
    2. Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk
      Pages 429-438
    3. Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest
      Pages 449-457
  12. Keynotes (Abstracts)

  13. Back Matter

About these proceedings


This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008.

The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.


CMOS DSP Filter FinFET active-mode leakage circuit analysis circuit design circuit optimization coloured petri net cryptography embedded system energy optimization energy saving field-effect transistor integrated circuit

Editors and affiliations

  • Lars Svensson
    • 1
  • José Monteiro
    • 2
  1. 1.Department of Computer EngineeringChalmers University of TechnologyGöteborgSweden
  2. 2.INESC-IDLisbonPortugal

Bibliographic information

  • DOI
  • Copyright Information Springer-Verlag Berlin Heidelberg 2009
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science Computer Science (R0)
  • Print ISBN 978-3-540-95947-2
  • Online ISBN 978-3-540-95948-9
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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