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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings

  • Editors
  • Nadine Azémard
  • Lars Svensson
Conference proceedings PATMOS 2007

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4644)

Table of contents

  1. Front Matter
  2. Session 1 - High-Level Design (1)

    1. Nicolas Fournel, Antoine Fraboulet, Paul Feautrier
      Pages 10-19
    2. Ioannis Panagopoulos, Christos Pavlatos, George Manis, George Papakonstantinou
      Pages 20-30
  3. Session 2 - Low Power Design Techniques

    1. Lai Mingche, Wang Zhiying, Guo JianJun, Dai Kui, Shen Li
      Pages 43-52
    2. Delong Shang, Chihoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeonghoon Oh et al.
      Pages 53-63
    3. Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
      Pages 75-85
    4. Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li
      Pages 86-96
  4. Session 3 - Low Power Analog Circuits

    1. Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
      Pages 107-116
  5. Session 4 - Statistical Static Timing Analysis

    1. Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma Vrudhula
      Pages 125-137
    2. V. Migairou, R. Wilson, S. Engels, Z. Wu, N. Azemard, P. Maurine
      Pages 138-147
    3. Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong R. Jiang, Yao-Wen Chang
      Pages 148-159
  6. Session 5 - Power Modeling and Optimization

    1. Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
      Pages 160-170
    2. Mandeep Singh, Christophe Giacomotto, Bart Zeydel, Vojin Oklobdzija
      Pages 181-190
    3. CR. Parthasarathy, A. Bravaix, C. Guérin, M. Denais, V. Huard
      Pages 191-200
  7. Session 6 - Low Power Routing Optimization

    1. Davide Pandini, Guido A. Repetto, Vincenzo Sinisi
      Pages 201-210
    2. Mini Nanua, David Blaauw
      Pages 211-221
    3. Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu
      Pages 222-231
  8. Session 7 - High Level Design (2)

    1. Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh
      Pages 255-267
    2. Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger
      Pages 268-277
    3. Sven Rosinger, Domenik Helms, Wolfgang Nebel
      Pages 278-287
    4. Allan Crone, Gabriel Chidolue
      Pages 288-299
    5. Zoltán Herczeg, Ákos Kiss, Daniel Schmidt, Norbert Wehn, Tibor Gyimóthy
      Pages 300-309
  9. Session 8 - Security and Asynchronous Design

    1. Maurice Keller, William Marnane
      Pages 310-319
    2. Jian Ruan, Zhiying Wang, Kui Dai, Yong Li
      Pages 320-329
    3. A. Razafindraibe, M. Robert, P. Maurine
      Pages 340-351
  10. Session 9 - Low Power Applications

    1. Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
      Pages 352-362
    2. Hendrik Eeckhaut, Harald Devos, Dirk Stroobandt
      Pages 363-372
    3. Miguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose M. Mendias, Dimitrios Soudris
      Pages 373-383
  11. Poster 1 - Modeling and Optimization

    1. Toshinori Sato, Yuji Kunitake
      Pages 384-393
    2. D. Guerrero, A. Millan, J. Juan, M. J. Bellido, P. Ruiz-de-Clavijo, E. Ostua et al.
      Pages 404-412
    3. Fabrice Guigues, Edith Kussener, Benjamin Duval, Hervé Barthelemy
      Pages 413-422
    4. Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui
      Pages 423-432
    5. Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss et al.
      Pages 433-442
  12. Poster 2 - High Level Design

    1. Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh
      Pages 443-452
    2. Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek J. Syrzycki
      Pages 453-462
    3. Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram
      Pages 463-473
    4. Paulo F. Butzen, André I. Reis, Chris H. Kim, Renato P. Ribas
      Pages 474-484
    5. Henrik Lipskoch, Karsten Albers, Frank Slomka
      Pages 495-504

About these proceedings

Introduction

th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

Keywords

CMOS DOM Transistor algorithms integrated circuits leakage optimization logic logic synthesis low power design metal-oxide-semiconductor transistor microarchitecture network architecture power consumption processor security

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-540-74442-9
  • Copyright Information Springer-Verlag Berlin Heidelberg 2007
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-74441-2
  • Online ISBN 978-3-540-74442-9
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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