© 2019

Post-Silicon Validation and Debug

  • Prabhat Mishra
  • Farimah Farahmandi

Table of contents

  1. Front Matter
    Pages i-xv
  2. Introduction

    1. Front Matter
      Pages 1-1
    2. Farimah Farahmandi, Prabhat Mishra
      Pages 3-16
  3. Debug Infrastructure

    1. Front Matter
      Pages 17-17
    2. Debapriya Chatterjee, Valeria Bertacco
      Pages 57-75
    3. Azadeh Davoodi
      Pages 77-85
    4. Alif Ahmed, Kamran Rahmani, Prabhat Mishra
      Pages 87-107
  4. Generation of Tests and Assertions

    1. Front Matter
      Pages 109-109
    2. Farimah Farahmandi, Prabhat Mishra
      Pages 111-123
    3. Xiaobing Shi, Nicola Nicolici
      Pages 125-144
    4. Pouya Taatizadeh, Nicola Nicolici
      Pages 179-208
  5. Post-Silicon Debug

    1. Front Matter
      Pages 209-209
    2. Sandeep Chandran, Preeti Ranjan Panda
      Pages 211-229
    3. Masahiro Fujita, Qinhao Wang, Yusuke Kimura
      Pages 231-253
    4. Georg Weissenbacher, Sharad Malik
      Pages 255-273
    5. Farimah Farahmandi, Prabhat Mishra
      Pages 307-321

About this book


This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts.  The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. 

  • Provides a comprehensive overview of the SoC post-silicon validation and debug challenges;
  • Covers state-of-the-art techniques for developing on-chip debug infrastructure;
  • Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis;
  • Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods;
  • Presents case studies for post-silicon debug of industrial SoC designs.


Post-silicon and Runtime Verification Trace-based Post-Silicon Validation On-chip Instrumentation Test Reduction for Quick Error Detection Post-silicon Debug Software

Editors and affiliations

  • Prabhat Mishra
    • 1
  • Farimah Farahmandi
    • 2
  1. 1.Department of Computer and Information Science and EngineeringUniversity of FloridaGainesvilleUSA
  2. 2.Department of Computer and Information Science and EngineeringUniversity of FloridaGainesvilleUSA

About the editors

Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida. His research interests include embedded and cyber-physical systems, energy-aware computing, hardware security and trust, system-on-chip verification, bioinformatics, and post-silicon validation and debug. He received his Ph.D. in Computer Science and Engineering from the University of California, Irvine. He has published six books and more than 150 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award, IBM Faculty Award, three best paper awards, and EDAA Outstanding Dissertation Award. Prof. Mishra currently serves as the Deputy Editor-in-Chief of IET Computers & Digital Techniques, and as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing. Currently, he is serving as the Program Chair of International Conference on VLSI Design and International Conference on Embedded Systems. He has served on many conference organizing committees and technical program committees of premier ACM and IEEE conferences. He is currently serving as an ACM Distinguished Speaker. Prof. Mishra is an ACM Distinguished Scientist and a Senior Member of IEEE.

Farimah Farahmandi received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran in 2010 and 2013, respectively. Her research is focused on developing analytical models and computational methods for design and verification of secure, trustworthy and energy-efficient systems. During her Ph.D., she has actively collaborated with various research groups (IBM, NXP, Intel, and Cisco) that have led to several joint publications. Her research has resulted in one book, six book chapters, and thirteen publications in premier ACM/IEEE journals and conferences. Her research has been recognized by several awards including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, nomination for Best Paper Award in ASPDAC 2017, DAC Richard Newton Young Student Fellowship, and SIGDA Ph.D. Forum at DAC. She was a research intern in advanced security research group at Cisco in summer 2016. 

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