© 2019

Formal Verification of Floating-Point Hardware Design

A Mathematical Approach


Table of contents

  1. Front Matter
    Pages i-xxiv
  2. Part I

    1. Front Matter
      Pages 1-1
    2. David M. Russinoff
      Pages 3-15
    3. David M. Russinoff
      Pages 17-37
    4. David M. Russinoff
      Pages 39-50
  3. Part II

    1. Front Matter
      Pages 51-52
    2. David M. Russinoff
      Pages 53-61
    3. David M. Russinoff
      Pages 63-75
    4. David M. Russinoff
      Pages 77-134
    5. David M. Russinoff
      Pages 135-144
  4. Part III

    1. Front Matter
      Pages 145-145
    2. David M. Russinoff
      Pages 147-163
    3. David M. Russinoff
      Pages 165-182
    4. David M. Russinoff
      Pages 183-202
    5. David M. Russinoff
      Pages 203-217
  5. Part IV

    1. Front Matter
      Pages 219-220
    2. David M. Russinoff
      Pages 221-226
    3. David M. Russinoff
      Pages 227-231
    4. David M. Russinoff
      Pages 233-236
  6. Part V

    1. Front Matter
      Pages 237-238

About this book


This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods.  Formal Verification of Floating-Point Hardware Design advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies.

 The book consists of five parts, the first two of which present a rigorous exposition of the general theory based on the first principles of arithmetic. Part I covers bit vectors and the bit manipulation primitives, integer and fixed-point encodings, and bit-wise logical operations.  Part II addresses the properties of floating-point numbers, the formats in which they are encoded as bit vectors, and the various modes of floating-point rounding.  In Part III, the theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations.  As a basis for the formal verification of such implementations, Part IV contains high-level specifications of correctness of the basic arithmetic instructions of several major industry-standard floating-point architectures, including all details pertaining to the handling of exceptional conditions.  Part V illustrates the methodology, applying the preceding theory to the comprehensive verification of a state-of-the-art commercial floating-point unit.

 All of these results have been formalized in the logic of the ACL2 theorem prover and mechanically checked to ensure their correctness.  They are presented here, however, in simple conventional mathematical notation.  The book presupposes no familiarity with ACL2, logic design, or any mathematics beyond basic high school algebra.  It will be of interest to verification engineers as well as arithmetic circuit designers who appreciate the value of a rigorous approach to their art, and is suitable as a graduate text in computer arithmetic.



floating-point arithmetic interactive theorem proving ACL2 formal verification computer aritmetic SRT division Booth multiplication formal specification of arithmetic instructions IEEE compliance

Authors and affiliations

  1. 1.Arm HoldingsAustinUSA

About the authors

David M. Russinoff is Principal Engineer at Arm Holdings. He holds a bachelor's degree from the Massachusetts Institute of Technology and a doctorate from New York University, both in mathematics, and a master's in computer sciences from the University of Texas at Austin.  He has spent twenty-five years developing mathematical methods of hardware verification, with an emphasis on interactive theorem proving, and applying them in the analysis of commercial designs, especially arithmetic circuits.  

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