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A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain

  • Introduces a new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain;

  • Describes innovative circuit topologies: the Voltage-Combiners biased OTA (supplied by a 3.3 V source); the Voltage-Combiners biased OTA with Current Starving, for higher gain and energy-efficiency (supplied by a 3.3 V source); the Folded Voltage-Combiners biased OTA (supplied by sources from 1.2 V to 0.9 V); and a Dynamic Voltage-Combiners biased OTA, for high performance analog-to-digital converters (supplied by a 1.2 V source);

  • Enables readers to reach better results than what is achievable with classic single-stage folded-cascode amplifiers, with state-of-the-art results in the context of dynamically biased amplifiers;

Book

Table of contents

  1. Front Matter
    Pages i-xvi
  2. Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta
    Pages 1-5
  3. Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta
    Pages 7-44
  4. Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta
    Pages 45-84
  5. Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta
    Pages 85-114
  6. Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta
    Pages 115-132
  7. Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta
    Pages 133-135
  8. Back Matter
    Pages 137-141

About this book

Introduction

This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation.  The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier.  Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family.

  • Introduces a new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain;
  • Describes innovative circuit topologies: the Voltage-Combiners biased OTA (supplied by a 3.3 V source); the Voltage-Combiners biased OTA with Current Starving, for higher gain and energy-efficiency (supplied by a 3.3 V source); the Folded Voltage-Combiners biased OTA (supplied by sources from 1.2 V to 0.9 V); and a Dynamic Voltage-Combiners biased OTA, for high performance analog-to-digital converters (supplied by a 1.2 V source);
  • Enables readers to reach better results than what is achievable with classic single-stage folded-cascode amplifiers, with state-of-the-art results in the context of dynamically biased amplifiers;




Keywords

Analog Amplifier Voltage-Combiners Dynamic, Switched-Capacitors Gain Enhancement Evolutionary Computation

Authors and affiliations

  1. 1.Instituto de Telecomunicações, Instituto Superior Técnico, Universidade de LisboaLisboaPortugal
  2. 2.UNINOVA, Faculdade de Ciências e Tecnologia, Universidade Nova de LisboaLisboaPortugal
  3. 3.Instituto de Telecomunicações, Instituto Superior Técnico, Universidade de LisboaLisboaPortugal

About the authors

Ricardo F. S. Póvoa is a Post-Doctoral Researcher in the Integrated Circuits Group, within the Instituto de Telecomunicações, Lisboa, Portugal.

João C. da Palma Goes is a Professor at Faculdade de Ciências e Tecnologia, Universidade Nova de Lisboa, Lisboa, Portugal.

Nuno C. G. Horta is a Professor at Instituto Superior Técnico, Universidade de Lisboa, and a Senior Researcher in the Integrated Circuits Group, within the Instituto de Telecomunicações, Lisboa, Portugal.

Bibliographic information

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