Advertisement

© 2018

Thread and Data Mapping for Multicore Systems

Improving Communication and Memory Accesses

Book

Part of the SpringerBriefs in Computer Science book series (BRIEFSCOMPUTER)

Table of contents

  1. Front Matter
    Pages i-ix
  2. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 1-8
  3. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 9-17
  4. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 19-34
  5. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 35-48
  6. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 49-49
  7. Back Matter
    Pages 51-54

About this book

Introduction

This book presents a study on how thread and data mapping techniques can be used to improve the  performance of multi-core architectures.

It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures.

On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access.

Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.

Keywords

Data Movement Thread Mapping Cache Memory Non-uniform memory access Data Mapping

Authors and affiliations

  1. 1.Federal Institute of Parana (IFPR)Paranavai, ParanaBrazil
  2. 2.University of Illinois at Urbana-ChampaignUrbanaUSA
  3. 3.Informatics InstituteFederal University of Rio Grande do Sul (UFRGS)Porto AlegreBrazil

About the authors

Eduardo Henrique Molina da Cruz graduated, with honors, in Computer Science in the State University of Maringá (UEM) in 2009. He received his master's degree from the Postgraduate Program in Computing in the Informatics Institute of the Federal University of Rio Grande do Sul (UFRGS) in 2012. In 2016, he received his Ph.D., with honors, also by the Postgraduate Program in Computing at the Informatics Institute of the Federal University of Rio Grande do Sul (UFRGS). After the Ph.D., he worked as a postdoctoral researcher at the Federal University of Rio Grande do Sul (UFRGS). His research comprises the areas of computer architecture, operating systems and parallel and distributed processing. It focuses on optimizing the memory access in multicore and manycore architectures, as well as architectures with non-uniform access to memory (NUMA). Currently, he is a professor at Federal Institute of Parana (IFPR).

Matthias Diener received his PhD degree in Computer Science from the Federal University of Rio Grande do Sul (UFRGS) and the TU Berlin in 2015. He is currently a postdoctoral researcher at the University of Illinois at Urbana-Champaign. His work focuses on adapting parallel applications to the hardware they are running on, through improving data locality, load balancing, and support for heterogeneous systems.

Philippe O. A. Navaux graduated in electronic engineering from UFRGS in 1970, and received the masters degree in applied physics from UFRGS in 1973 and the Ph.D. degree in computer science from INPG, France in 1979. He is a professor at UFRGS since 1973. He is the head of the Parallel and Distributed Processing Group at UFRGS and a consultant to various national and international funding agencies such as DoE (US), ANR (FR), CNPq, and CAPES (BR).

Bibliographic information

  • Book Title Thread and Data Mapping for Multicore Systems
  • Book Subtitle Improving Communication and Memory Accesses
  • Authors Eduardo H. M. Cruz
    Matthias Diener
    Philippe O. A. Navaux
  • Series Title SpringerBriefs in Computer Science
  • Series Abbreviated Title SpringerBriefs Computer Sci.
  • DOI https://doi.org/10.1007/978-3-319-91074-1
  • Copyright Information The Author(s), under exclusive licence to Springer International Publishing AG, part of Springer Nature 2018
  • Publisher Name Springer, Cham
  • eBook Packages Computer Science Computer Science (R0)
  • Softcover ISBN 978-3-319-91073-4
  • eBook ISBN 978-3-319-91074-1
  • Series ISSN 2191-5768
  • Series E-ISSN 2191-5776
  • Edition Number 1
  • Number of Pages IX, 54
  • Number of Illustrations 34 b/w illustrations, 0 illustrations in colour
  • Topics Computer Hardware
    Software Engineering/Programming and Operating Systems
  • Buy this book on publisher's site
Industry Sectors
Electronics
IT & Software
Telecommunications