© 2018

Timing Performance of Nanometer Digital Circuits Under Process Variations


Part of the Frontiers in Electronic Testing book series (FRET, volume 39)

Table of contents

  1. Front Matter
    Pages i-xviii
  2. Victor Champac, Jose Garcia Gervacio
    Pages 1-17
  3. Victor Champac, Jose Garcia Gervacio
    Pages 19-39
  4. Victor Champac, Jose Garcia Gervacio
    Pages 41-69
  5. Victor Champac, Jose Garcia Gervacio
    Pages 71-95
  6. Victor Champac, Jose Garcia Gervacio
    Pages 97-118
  7. Victor Champac, Jose Garcia Gervacio
    Pages 119-141
  8. Victor Champac, Jose Garcia Gervacio
    Pages 143-163
  9. Back Matter
    Pages 165-185

About this book


This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations.  Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications.  Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.


Process Variations and Probabilistic Integrated Circuit Design Variation-Aware Design of Custom Integrated Circuits Statistical Performance Modeling and Optimization Yield and Variability Optimization of Integrated Circuits Statistical Analysis and Optimization for VLSI

Authors and affiliations

  1. 1.INAOETonantzintlaMexico
  2. 2.Universidad VeracruzanaXalapaMexico

About the authors

Victor Champac received the Electrical Engineering Degree in 1987 from the Autonomous University of Nuevo Leon, Mexico. He received the Ph.D. degree in 1993 from the Polytechnic University of Catalonia (UPC), Spain. From 1988 to 1993 he was Associate Professor at the Electronic Engineering Department of the UPC. In 1993 he joined the National Institute for Astrophysics, Optics and Electronics (INAOE) in Mexico where he is Titular Professor. He made sabbatical in 2001-2002 at Motorola and in 2010-2011 at the University of California (UCSD). Dr. Champac was a co-founder of the Test Technology Technical Council-Latin America of IEEE Computer Society.  He was co-General Chair of the 2nd, 9th, 13th and 16th IEEE Latin-American Test Workshop (now Latin-American Test Symposium). He has also served as Guest Editor of the Journal of Electronics Testing, Springer. He is member of the Editorial Board of Journal of Electronic Testing (JETTA).  He is a Senior member of the IEEE and the National Research System (SNI) in Mexico. He has served as program and organizing committee member of several international conferences. Dr. Champac received the best paper award of the IEEE Latin American Test Workshop in 2008. He has published more than 120 papers in international journals and conferences. His research lines include: circuit design under process variations, aging reliable circuit design, defect modeling in leading technologies, and development of new test strategies. 

Jose Garcia Gervacio received the Electronics Engineering Degree in 1987 from the Technological Institute of Celaya, Mexico. He received the Master and Ph.D. degree in 2003 and 2009, respectively, from the National Institute for Astrophysics, Optics, and Electronics (INAOE), Mexico. From 2010 to 2011 he was an assistant professor at INAOE. From 2011 to 2013 he occupied a postdoctoral position in the Research center in Micro and Nanotechnology (MICRONA) of the University Veracruzana. Since 2013 he is Full-time Professor of the  University Veracruzana in Xalapa, Mexico. He has served as program and organizing committee member of the 4th Biannual European - Latin American Summer School on Design, Test, and Reliability (BELAS-2015). He served as organizing committee member of the 16th IEEE Latin American Test Symposium (LATS-2015). His research interest is focused on the design and testing of VLSI digital circuits. 




Bibliographic information

  • Book Title Timing Performance of Nanometer Digital Circuits Under Process Variations
  • Authors Victor Champac
    Jose Garcia Gervacio
  • Series Title Frontiers in Electronic Testing
  • Series Abbreviated Title Frontiers Electronic Test
  • DOI
  • Copyright Information Springer International Publishing AG, part of Springer Nature 2018
  • Publisher Name Springer, Cham
  • eBook Packages Engineering Engineering (R0)
  • Hardcover ISBN 978-3-319-75464-2
  • Softcover ISBN 978-3-030-09239-9
  • eBook ISBN 978-3-319-75465-9
  • Series ISSN 0929-1296
  • Edition Number 1
  • Number of Pages XVIII, 185
  • Number of Illustrations 25 b/w illustrations, 91 illustrations in colour
  • Topics Circuits and Systems
    Processor Architectures
    Electronics and Microelectronics, Instrumentation
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