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Parasitic Substrate Coupling in High Voltage Integrated Circuits

Minority and Majority Carriers Propagation in Semiconductor Substrate

  • Pietro Buccella
  • Camillo Stefanucci
  • Maher Kayal
  • Jean-Michel Sallese

Part of the Analog Circuits and Signal Processing book series (ACSP)

Table of contents

  1. Front Matter
    Pages i-xvii
  2. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 1-9
  3. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 11-39
  4. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 41-68
  5. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 69-96
  6. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 97-112
  7. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 113-143
  8. Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
    Pages 145-174
  9. Back Matter
    Pages 175-183

About this book

Introduction

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.

The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.

The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.


  • Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
  • Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
  • Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
  • Offers design guidelines to reduce couplings by adding specific test protections.

Keywords

Parasitic failures in integrated circuits Substrate Noise Coupling in RFICs substrate parasitic bipolar transistors Smart Power ICs ESD protection

Authors and affiliations

  • Pietro Buccella
    • 1
  • Camillo Stefanucci
    • 2
  • Maher Kayal
    • 3
  • Jean-Michel Sallese
    • 4
  1. 1.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  3. 3.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  4. 4.STI IEL EDALBÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-74382-0
  • Copyright Information Springer International Publishing AG, part of Springer Nature 2018
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-74381-3
  • Online ISBN 978-3-319-74382-0
  • Series Print ISSN 1872-082X
  • Series Online ISSN 2197-1854
  • Buy this book on publisher's site
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