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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

  • Pascal Meinerzhagen
  • Adam Teman
  • Robert Giterman
  • Noa Edri
  • Andreas Burg
  • Alexander Fish

Table of contents

  1. Front Matter
    Pages i-ix
  2. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 1-12
  3. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 13-26
  4. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 27-48
  5. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 49-59
  6. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 61-90
  7. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 91-111
  8. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 113-134
  9. Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
    Pages 135-139
  10. Back Matter
    Pages 141-146

About this book

Introduction

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

Keywords

Memory Systems Memory for VLSI embedded DRAM memory embedded memory design memory optimization error-tolerant embedded memory

Authors and affiliations

  • Pascal Meinerzhagen
    • 1
  • Adam Teman
    • 2
  • Robert Giterman
    • 3
  • Noa Edri
    • 4
  • Andreas Burg
    • 5
  • Alexander Fish
    • 6
  1. 1.Intel Labs, Circuit Research LabIntel CorporationHillsboroUSA
  2. 2.Faculty of EngineeringBar-Ilan UniversityRamat GanIsrael
  3. 3.Faculty of EngineeringBar-Ilan UniversityRamat GanIsrael
  4. 4.Faculty of EngineeringBar-Ilan UniversityRamat GanIsrael
  5. 5.EPFL STI IEL TCLLausanneSwitzerland
  6. 6.Faculty of EngineeringBar-Ilan UniversityRamat GanIsrael

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-60402-2
  • Copyright Information Springer International Publishing AG 2018
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-60401-5
  • Online ISBN 978-3-319-60402-2
  • Buy this book on publisher's site
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