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From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators

Benefits

  • Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction

  • Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability

  • Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators

Book
  • 5.9k Downloads

Table of contents

  1. Front Matter
    Pages i-xv
  2. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
    Pages 1-7
  3. Predicting and Preventing Errors

    1. Front Matter
      Pages 9-9
    2. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 11-19
    3. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 21-46
    4. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 47-60
    5. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 61-74
    6. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 75-88
  4. Detecting and Correcting Errors

    1. Front Matter
      Pages 89-90
    2. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 91-115
    3. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 117-130
  5. Accepting Errors

    1. Front Matter
      Pages 131-132
    2. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 133-149
    3. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 151-164
    4. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 165-179
    5. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 181-190
    6. Abbas Rahimi, Luca Benini, Rajesh K. Gupta
      Pages 191-193
  6. Back Matter
    Pages 195-197

About this book

Introduction

This book focuses on computing devices and their design at various levels to combat variability.  The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience.

  • ·         Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction;
  • ·         Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability;
  • ·         Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators.

Keywords

Analysis and Design of Resilient VLSI Circuits Variation-Tolerant Design in Nanometer Silicon Variation Tolerant VLSI Designs microelectronic variability combating variability

Authors and affiliations

  1. 1.Department of Electrical Engineering and Computer SciencesUniversity of California BerkeleyBerkeleyUSA
  2. 2.Integrated Systems LaboratoryETH ZurichZürichSwitzerland
  3. 3.Department of Computer Science and EngineeringUniversity of California, San DiegoLa JollaUSA

About the authors

Abbas Rahimi is currently a Postdoctoral Scholar in the Department of Electrical Engineering and Computer Sciences at the University of California Berkeley, Berkeley, CA, USA. He is a member of the Berkeley Wireless Research Center and collaborating with UC Berkeley’s Redwood Center for Theoretical Neuroscience. Rahimi has a B.S. in computer engineering from the University of Tehran, Tehran, Iran (2010) and an M.S. and a Ph.D. in computer science and engineering from the University of California San Diego, La Jolla, CA, USA (2015). His research interests include brain-inspired computing, approximate computing, massively parallel integrated architectures, embedded systems and software with an emphasis on improving energy efficiency and robustness. His doctoral dissertation has been selected to receive the 2015 Outstanding Dissertation Award in the area of "New Directions in Embedded System Design and Embedded Software" from the European Design and Automation Association. He has published more than 40 papers in top tier conferences and journals, and received the Best Paper Candidate at 50th IEEE/ACM Design Automation Conference.

Luca Benini is a Professor of Digital Circuits and Systems at ETH Zurich, Switzerland, and is also a Professor at University of Bologna, Italy. He has a PhD in Electrical Engineering from Stanford University (1997). His research interests are in energy-efficient system design and multicore SoC design. He is a Fellow of both IEEE and ACM, and  member of the Academia Europea.

Rajesh K. Gupta is a Professor of Computer Science and Engineering at the University of California San Diego (UCSD), La Jolla, CA, USA and holds the Qualcomm endowed chair. Gupta has a BTech in electrical engineering from the Indian Institute of Technology, Kanpur, India (1984), an MS in electrical engineering and computer science from the University of California Berkeley, Berkeley, CA, USA (1986), and a PhD in electrical engineering from Stanford University, Stanford, CA, USA (1994). He is a Fellow of both IEEE and ACM.

Bibliographic information

  • Book Title From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators
  • Authors Abbas Rahimi
    Luca Benini
    Rajesh K. Gupta
  • DOI https://doi.org/10.1007/978-3-319-53768-9
  • Copyright Information Springer International Publishing AG 2017
  • Publisher Name Springer, Cham
  • eBook Packages Engineering Engineering (R0)
  • Hardcover ISBN 978-3-319-53767-2
  • Softcover ISBN 978-3-319-85239-3
  • eBook ISBN 978-3-319-53768-9
  • Edition Number 1
  • Number of Pages XV, 197
  • Number of Illustrations 38 b/w illustrations, 48 illustrations in colour
  • Topics Circuits and Systems
    Processor Architectures
    Logic Design
  • Buy this book on publisher's site
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