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Analysis and Design of Networks-on-Chip Under High Process Variation

  • Rabab Ezz-Eldin
  • Magdy Ali El-Moursy
  • Hesham F. A. Hamed
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Table of contents

  1. Front Matter
    Pages i-xxi
  2. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
    Pages 1-7
  3. Background

    1. Front Matter
      Pages 9-9
    2. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 11-44
    3. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 45-56
    4. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 57-68
  4. Impact of Process Variation on Low and High Levels Designs

    1. Front Matter
      Pages 69-69
    2. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 71-86
    3. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 87-97
  5. Simulation Results and Future Work

    1. Front Matter
      Pages 99-99
    2. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 101-119
    3. Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
      Pages 121-123
  6. Back Matter
    Pages 125-141

About this book

Introduction

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.


  • Demonstrates the impact of process variation on Networks-on-Chip of different topologies; 
  • Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms;
  • Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr

opriate output path based on process variation and congestion.

Keywords

Asynchronous Noc Design Under High Process Variation Interconnection networks on chip Network-on-Chip Network-on-Chip routing architectures NoC Process Variation-Aware Routing in NoC Based Multicores

Authors and affiliations

  • Rabab Ezz-Eldin
    • 1
  • Magdy Ali El-Moursy
    • 2
  • Hesham F. A. Hamed
    • 3
  1. 1.Electrical Engineering DepartmentBeni-Suef UniversityBani SweifEgypt
  2. 2.Electronics Research InstituteCairoEgypt
  3. 3.Electrical Engineering DepartmentMinia UniversityMinyaEgypt

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