IP Cores Design from Specifications to Production

Modeling, Verification, Optimization, and Protection

  • Khaled Salah Mohamed

Part of the Analog Circuits and Signal Processing book series (ACSP)

Table of contents

About this book

Introduction

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies.

·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;

·         Introduce a deep introduction for Verilog for both implementation and verification point of view. 

·         Demonstrates how to use IP in applications such as memory controllers and SoC buses.

·         Describes a new verification methodology called bug localization;

·         Presents a novel scan-chain methodology for RTL debugging;

·         Enables readers to employ UVM methodology in straightforward, practical terms.

Keywords

IP Cores Design IP lifecycle IP-Based Design Modern VLSI Design RTL debugging SoC Verification UVM methodology

Authors and affiliations

  • Khaled Salah Mohamed
    • 1
  1. 1.EmulationMentor GraphicsHeliopolisEgypt

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-22035-2
  • Copyright Information Springer International Publishing Switzerland 2016
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-22034-5
  • Online ISBN 978-3-319-22035-2
  • Series Print ISSN 1872-082X
  • Series Online ISSN 2197-1854
  • About this book
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