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Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies

  • António Manuel Lourenço Canelas
  • Jorge Manuel Correia Guilherme
  • Nuno Cavaco Gomes Horta
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Table of contents

  1. Front Matter
    Pages i-xxiii
  2. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 1-7
  3. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 9-64
  4. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 65-95
  5. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 97-153
  6. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 155-177
  7. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 179-224
  8. António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
    Pages 225-230
  9. Back Matter
    Pages 231-237

About this book

Introduction

This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations.  The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population.  In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization.

  • Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms;
  • Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow;
  • Includes detailed background on automatic analog IC sizing and optimization.

Keywords

Variation-Aware Design of Custom Integrated Circuits Analog Design Centering and Sizing Analog IC Reliability in Nanometer CMOS analog integrated circuit yield estimation Monte Carlo-Based Yield Estimation

Authors and affiliations

  • António Manuel Lourenço Canelas
    • 1
  • Jorge Manuel Correia Guilherme
    • 2
  • Nuno Cavaco Gomes Horta
    • 3
  1. 1.Instituto Superior TécnicoInstituto de TelecomunicaçõesLisbonPortugal
  2. 2.Instituto Politécnico de TomarInstituto de TelecomunicaçõesLisbonPortugal
  3. 3.Instituto Superior TécnicoInstituto de TelecomunicaçõesLisbonPortugal

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-030-41536-5
  • Copyright Information Springer Nature Switzerland AG 2020
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-030-41535-8
  • Online ISBN 978-3-030-41536-5
  • Buy this book on publisher's site
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