© 2020

The Fourth Terminal

Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems

  • Sylvain Clerc
  • Thierry Di Gilio
  • Andreia Cathelin

Part of the Integrated Circuits and Systems book series (ICIR)

Table of contents

  1. Front Matter
    Pages i-xvi
  2. Andreia Cathelin, Sylvain Clerc
    Pages 1-6
  3. Device Level and General Studies for Analog and Digital

    1. Front Matter
      Pages 7-7
    2. Franck Arnaud
      Pages 9-57
    3. Sylvain Clerc, Ricardo Gomez Gomez
      Pages 59-83
    4. Lorenzo Ciampolini
      Pages 93-115
  4. Design Examples: From Analog RF and mmW to Digital. From Building Blocks and Circuits to SoCs

    1. Front Matter
      Pages 117-117
    2. Ilias Sourikopoulos, Andreia Cathelin, Andreas Kaiser, Antoine Frappé
      Pages 119-134
    3. Raphaël Guillaume, Andreia Cathelin, Yann Deval
      Pages 135-168
    4. Florent Torres, Andreia Cathelin, Eric Kerhervé
      Pages 169-222
    5. Martin Cochet, Ben Keller, Sylvain Clerc, Fady Abouzeid, Andreia Cathelin, Jean-Luc Autran et al.
      Pages 243-261
    6. Ben Keller, Borivoje Nikolić, Brian Zimmer, Martin Cochet, Yunsup Lee, Jaehwa Kwak et al.
      Pages 263-302
  5. Body-Bias Deployment in Mixed-Signal and Digital SoCs

    1. Front Matter
      Pages 303-303
    2. Ricardo Gomez Gomez, Sylvain Clerc
      Pages 305-325
    3. Sylvain Clerc, Ricardo Gomez Gomez
      Pages 327-331
    4. Ricardo Gomez Gomez
      Pages 333-349
    5. Thierry Di Gilio
      Pages 351-384
    6. Sébastien Marchal, Damien Riquet, Sylvain Clerc
      Pages 385-394

About this book


This book discusses the advantages and challenges of Body-Biasing for integrated circuits and systems, together with the deployment of the design infrastructure needed to generate this Body-Bias voltage. These new design solutions enable state of the art energy efficiency and system flexibility for the latest applications, such as Internet of Things and 5G communications.

  • Provides readers with a single-source reference to Body-Biasing Techniques for FDSOI Circuits and Systems;
  • Describes integrated circuit design techniques specific to deep submicron Ultra Thin Body and Box Fully-Depleted Silicon on Insulator CMOS technology;
  • Presents the first coherent collection of FDSOI specific design techniques, for applications ranging from analog, RF, mmW to SRAM design, embedded power management and energy efficient digital design.


Deep submicron integrated circuit design Silicon-On-Insulator Semiconductor-On-Insulator Ultra Thin Body and Box Fully-Depleted Silicon on Insulator UTBB FDSOI CMOS

Editors and affiliations

  • Sylvain Clerc
    • 1
  • Thierry Di Gilio
    • 2
  • Andreia Cathelin
    • 3
  1. 1.STMicroelectronicsCrollesFrance
  2. 2.STMicroelectronicsCrollesFrance
  3. 3.STMicroelectronicsCrollesFrance

About the editors

Sylvain CLERC (M'99) received the Engineering Degree in Digital System Architecture from Grenoble National Polytechnical Institute in 1993. From 1995 to 1999 he was with Dolphin Integration, now Dolphin Design, Meylan, France, working on memory generator design and automated layout. In 1999, he joined STMicroelectronics, Crolles, France, in Technology Design Platform group. He was responsible for standard cell design and Silicon qualification. From 2006 to 2016 he was in a team in charge of radiation hardening and silicon IPs qualification for space and terrestrial environments. He is now working in Digital Design Flow Methodology team. His current research domain is Safety and Energy Efficient circuit design.

Thierry DI GILIO was born in 1978 in Marseille, France. He received his his M.Sc in Physic and Modelling Of complex Systems from University of Provence, France in 2002. In 2006, he obtained his PhD degree in nano-electronic from University of Provence. During 3 years, he worked at Sofradir (Veurey-Voroise, France) as a consultant, and designed several Readout Circuits for  cooled infrared detector applications. In 2011 he joined STMicroelectronics Central R&D (in Crolles, France) to design embedded power management circuits for digital and RF SoCs including the development of embedded boby biasing solutions for FDSOI technologies. He is now in charge of Power Management IP design within Imaging Product group.

Andreia Cathelin (M’04, SM’11) is a Technology R&D Fellow at STMicroelectronics, Crolles France.  She started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d’Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France. 

Since 1998, she has been with STMicroelectronics, Crolles, France. Her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is leading and driving advanced R&D research topics, also in collaboration with major research teams from Universities worldwide. She is as well one of the pioneers worldwide in FD-SOI CMOS design.

Andreia has had numerous responsibilities inside the IEEE community since more than 10 years. At ISSCC, she has been the RF sub-committee chair from 2012 to 2015, and since 2016 is the Forums Chair and member of the Executive Committee.  She has been the ESSCIRC-ESSDERC Steering Committee Chair from 2015 to 2017 and is the Technical Program Chair for ESSCIRC2020. She has served different positions on the Technical Program Committees of VLSI Symposium on Circuits from 2010 till 2016, and is now member of its Executive Committee.  She has been an elected member of the IEEE SSCS Adcom for the term January 2015 to December 2017 and for the 2020-2022 term, and is an active member of the IEEE SSCS Women in Circuits group.

Andreia has authored or co-authored 130+ technical papers and 7 book chapters and has filed more than 25 patents. She is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper and of the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper. She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, for having introduced on the company’s roadmap the integrated CMOS THz technology for imaging applications.

Bibliographic information

  • Book Title The Fourth Terminal
  • Book Subtitle Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems
  • Editors Sylvain Clerc
    Thierry Di Gilio
    Andreia Cathelin
  • Series Title Integrated Circuits and Systems
  • Series Abbreviated Title Integrated Circuits,Systems
  • DOI
  • Copyright Information Springer Nature Switzerland AG 2020
  • Publisher Name Springer, Cham
  • eBook Packages Engineering Engineering (R0)
  • Hardcover ISBN 978-3-030-39495-0
  • Softcover ISBN 978-3-030-39498-1
  • eBook ISBN 978-3-030-39496-7
  • Series ISSN 1558-9412
  • Series E-ISSN 1558-9420
  • Edition Number 1
  • Number of Pages XVI, 431
  • Number of Illustrations 54 b/w illustrations, 284 illustrations in colour
  • Topics Circuits and Systems
    Electronic Circuits and Devices
    Processor Architectures
  • Buy this book on publisher's site
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