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System-on-Chip Security

Validation and Verification

  • Farimah Farahmandi
  • Yuanwen Huang
  • Prabhat Mishra
Book

Table of contents

  1. Front Matter
    Pages i-xix
  2. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 1-13
  3. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 15-35
  4. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 37-57
  5. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 59-97
  6. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 99-114
  7. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 115-135
  8. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 137-152
  9. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 153-171
  10. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 173-188
  11. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 189-219
  12. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 221-271
  13. Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
    Pages 273-279
  14. Back Matter
    Pages 281-289

About this book

Introduction

This book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle.  The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches.  This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs.

  • Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle;
  • Summarizes unsafe current design practices that lead to security and trust vulnerabilities;
  • Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers;
  • Explains how to leverage security validation approaches to prevent side-channel attacks;
  • Presents automated debugging and patching techniques in the presence of security vulnerabilities;
  • Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.

Keywords

Hardware IP Security and Trust Hardware Trojan Hardware Security Hardware Security Verification Hardware Security Validation

Authors and affiliations

  • Farimah Farahmandi
    • 1
  • Yuanwen Huang
    • 2
  • Prabhat Mishra
    • 3
  1. 1.University of FloridaGainesvilleUSA
  2. 2.GoogleMountain ViewUSA
  3. 3.University of FloridaGainesvilleUSA

Bibliographic information

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