FPGA-BASED Hardware Accelerators

  • Iouliia Skliarova
  • Valery Sklyarov

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 566)

Table of contents

  1. Front Matter
    Pages i-xvi
  2. Iouliia Skliarova, Valery Sklyarov
    Pages 1-38
  3. Iouliia Skliarova, Valery Sklyarov
    Pages 39-67
  4. Iouliia Skliarova, Valery Sklyarov
    Pages 69-103
  5. Iouliia Skliarova, Valery Sklyarov
    Pages 105-160
  6. Iouliia Skliarova, Valery Sklyarov
    Pages 161-212
  7. Iouliia Skliarova, Valery Sklyarov
    Pages 213-241
  8. Back Matter
    Pages 243-245

About this book


This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.


FPGA Optimization Techniques Data Processing Combinatorial Optimization Hardware Accelerators Xilinx

Authors and affiliations

  • Iouliia Skliarova
    • 1
  • Valery Sklyarov
    • 2
  1. 1.Department of Electronics Telecommunications and InformaticsUniversity of AveiroAveiroPortugal
  2. 2.Department of Electronics Telecommunications and InformaticsUniversity of AveiroAveiroPortugal

Bibliographic information

  • DOI
  • Copyright Information Springer Nature Switzerland AG 2019
  • Publisher Name Springer, Cham
  • eBook Packages Engineering Engineering (R0)
  • Print ISBN 978-3-030-20720-5
  • Online ISBN 978-3-030-20721-2
  • Series Print ISSN 1876-1100
  • Series Online ISSN 1876-1119
  • Buy this book on publisher's site
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