About this book
This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.
- Addresses practical design issues and their workarounds;
- Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine;
- Provides readers with an RTL coding guideline, based on real experience.
VLSI Physical Design Automation CMOS VLSI Design VLSI Verification VLSI Testing Design For Test
- DOI https://doi.org/10.1007/978-3-030-03238-8
- Copyright Information Springer Nature Switzerland AG 2019
- Publisher Name Springer, Cham
- eBook Packages Engineering
- Print ISBN 978-3-030-03237-1
- Online ISBN 978-3-030-03238-8
- Buy this book on publisher's site