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On Optimal Interconnections for VLSI

  • Andrew B. Kahng
  • Gabriel Robins

Table of contents

  1. Front Matter
    Pages i-xvii
  2. Andrew B. Kahng, Gabriel Robins
    Pages 1-15
  3. Andrew B. Kahng, Gabriel Robins
    Pages 16-63
  4. Andrew B. Kahng, Gabriel Robins
    Pages 64-139
  5. Andrew B. Kahng, Gabriel Robins
    Pages 140-196
  6. Andrew B. Kahng, Gabriel Robins
    Pages 197-238
  7. Back Matter
    Pages 239-286

About this book

Introduction

On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts.
Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design.

Keywords

FPGA Field Programmable Gate Array Phase Signal VLSI algorithms circuit circuit design computer-aided design (CAD) construction development interconnect layout packaging tables

Authors and affiliations

  • Andrew B. Kahng
    • 1
  • Gabriel Robins
    • 2
  1. 1.University of CaliforniaLos AngelesUSA
  2. 2.University of VirginiaUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4757-2363-2
  • Copyright Information Springer-Verlag US 1995
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4419-5145-8
  • Online ISBN 978-1-4757-2363-2
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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