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Latchup in CMOS Technology

The Problem and Its Cure

  • Ronald R. Troutman

Table of contents

  1. Front Matter
    Pages i-xxi
  2. Ronald R. Troutman
    Pages 1-6
  3. Ronald R. Troutman
    Pages 7-21
  4. Ronald R. Troutman
    Pages 23-36
  5. Ronald R. Troutman
    Pages 37-116
  6. Ronald R. Troutman
    Pages 117-164
  7. Ronald R. Troutman
    Pages 165-196
  8. Ronald R. Troutman
    Pages 197-207
  9. Back Matter
    Pages 209-243

About this book

Introduction

Why a book on Iatchup? Latchup has been, and continues to be, a potentially serious CMOS reliability concern. This concern is becoming more widespread with the ascendency of CMOS as the dominant VLSI technology, particularly as parasitic bipolar characteristics continue to improve at ever smaller dimensions on silicon wafers with ever lower defect densities. Although many successful parts have been marketed, latchup solutions have often been ad hoc. Although latchup avoidance techniques have been previously itemized, there has been little quantitative evaluation of prior latchup fixes. What is needed is a more general, more systematic treatment of the latchup problem. Because of the wide variety of CMOS technologies and the long term interest in latchup, some overall guiding principles are needed. Appreciating the variety of possible triggering mechanisms is key to a real understanding of latchup. This work reviews the origin of each and its effect on the parasitic structure. Each triggering mechanism is classified according to a new taxonomy.

Keywords

CMOS Potential VLSI Wafer stability

Authors and affiliations

  • Ronald R. Troutman
    • 1
  1. 1.IBM CorporationUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4757-1887-4
  • Copyright Information Springer-Verlag US 1986
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4419-5199-1
  • Online ISBN 978-1-4757-1887-4
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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