Defect and Fault Tolerance in VLSI Systems

Volume 1

  • Israel Koren

Table of contents

  1. Front Matter
    Pages i-xii
  2. Yield Models for Defect-Tolerant Vlsi Circuits: A Review

    1. Israel Koren, Charles H. Stapper
      Pages 1-21
  3. Wafer Scale Revisited

    1. Douglas L. Peltzer
      Pages 23-31
  4. Models for Defects and Yield

    1. A. V. Ferris-Prabhu
      Pages 33-46
    2. Sharad C. Seth, Vishwani D. Agrawal
      Pages 47-52
    3. C. Thibeault, Y. Savaria, J.-L. Houle
      Pages 53-64
  5. Defect-Tolerant Designs

    1. Michael C. Howells, Robert Aitken, Vinod K. Agarwal
      Pages 65-76
    2. R. J. Cosentino, B. L. Johnson, J. J. Vaccaro
      Pages 77-84
  6. Defect Monitoring and Yield Projection

  7. Testing and Testable Designs

    1. Koichi Yamashita, Shinpei Hijiya, Gensuke Goto, Nobutake Matsumura
      Pages 139-148
    2. Donald Fussell, Sampath Rangarajan, Miroslaw Malek
      Pages 149-160
    3. Michal Cutler, Minghsien Wang, Stephen Y. H. Su
      Pages 161-170
  8. Defect- and Fault-Tolerant Processors

    1. B. Maytal, A. Danor, V. Karpati, R. Nassrallah, Y. Sidi, E. Shihadeh
      Pages 171-177
    2. Regis Leveugle, Mohammad Soueidan, Norbert Wehn
      Pages 179-190
    3. Savio Chau, David Rennels
      Pages 191-202
  9. Defect- and Fault-Tolerant Memories

    1. B. Nasreddine, E.-F. Kouka, Y. Wang, D. Marron, J. Trilhe
      Pages 227-242
    2. C. A. Njinda, C. G. Guy, W. R. Moore
      Pages 257-267
  10. Reconfigurable Arrays

  11. Fault-Tolerant Arrays

    1. G. Saucier, J.-L. Patry, E.-F. Kouka, T. Midwinter, P. Ivey, M. Huch et al.
      Pages 327-338
  12. Back Matter
    Pages 357-362

About this book


This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition­ ers from both industry and academia in the field of defect tolerance and yield en­ ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.


Area VLSI algorithms architecture architectures distribution field forum forums information integrated circuit object review selection society

Editors and affiliations

  • Israel Koren
    • 1
  1. 1.University of MassachusettsAmherstUSA

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