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Reuse Methodology Manual

For System-on-a-Chip Designs

  • Michael Keating
  • Pierre Bricaud

Table of contents

  1. Front Matter
    Pages i-xxiii
  2. Michael Keating, Pierre Bricaud
    Pages 1-10
  3. Michael Keating, Pierre Bricaud
    Pages 11-24
  4. Michael Keating, Pierre Bricaud
    Pages 25-52
  5. Michael Keating, Pierre Bricaud
    Pages 53-72
  6. Michael Keating, Pierre Bricaud
    Pages 73-125
  7. Michael Keating, Pierre Bricaud
    Pages 127-143
  8. Michael Keating, Pierre Bricaud
    Pages 145-170
  9. Michael Keating, Pierre Bricaud
    Pages 171-197
  10. Michael Keating, Pierre Bricaud
    Pages 199-206
  11. Michael Keating, Pierre Bricaud
    Pages 207-228
  12. Michael Keating, Pierre Bricaud
    Pages 229-251
  13. Michael Keating, Pierre Bricaud
    Pages 253-259
  14. Michael Keating, Pierre Bricaud
    Pages 261-276
  15. Back Matter
    Pages 277-286

About this book

Introduction

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available.
These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity.
Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.

Keywords

ASIC RTL Scratch integrated circuit system on chip (SoC) transistor

Authors and affiliations

  • Michael Keating
    • 1
  • Pierre Bricaud
    • 2
  1. 1.Synopsys, Inc.USA
  2. 2.Mentor Graphics CorporationUSA

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