Advertisement

Optimal VLSI Architectural Synthesis

Area, Performance and Testability

  • Catherine H. Gebotys
  • Mohamed I. Elmasry

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 158)

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Introduction

    1. Front Matter
      Pages 1-1
    2. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 3-20
    3. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 21-36
  3. Review and Background

    1. Front Matter
      Pages 37-37
    2. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 39-61
    3. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 63-80
  4. Optimal Architectural Synthesis with Interfaces

    1. Front Matter
      Pages 81-81
    2. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 83-95
    3. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 97-108
    4. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 109-122
    5. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 123-128
    6. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 129-140
    7. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 141-175
  5. Testable Architectural Synthesis

    1. Front Matter
      Pages 177-177
    2. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 179-205
    3. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 207-258
  6. Summary and Future Research

    1. Front Matter
      Pages 259-259
    2. Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 261-270
  7. Back Matter
    Pages 271-289

About this book

Introduction

Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there­ fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo­ rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn­ thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.

Keywords

VLSI algorithms analog architecture complexity computer design process filter integrated circuit model network optimization programming stability testing

Authors and affiliations

  • Catherine H. Gebotys
    • 1
  • Mohamed I. Elmasry
    • 1
  1. 1.University of WaterlooWaterlooCanada

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-4018-2
  • Copyright Information Kluwer Academic Publishers 1992
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6797-0
  • Online ISBN 978-1-4615-4018-2
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
Industry Sectors
Automotive
Electronics
IT & Software
Telecommunications
Energy, Utilities & Environment
Aerospace
Oil, Gas & Geosciences
Engineering