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Parallel Algorithms and Architectures for DSP Applications

  • Magdy A. Bayoumi

Table of contents

  1. Front Matter
    Pages i-xiii
  2. M. Sarrafzadeh, A. K. Katsaggelos, S. P. R. Kumar
    Pages 1-31
  3. George B. Adams III, Edward C. Bronson, Thomas L. Casavant, Leah H. Jamieson, Ray A. Kamin III
    Pages 49-75
  4. K. J. R. Liu, S. F. Hsieh
    Pages 77-112
  5. Björn Lisper, Sanjay Rajopadhye
    Pages 129-158
  6. Edward Ashford Lee, Jeffrey C. Bier
    Pages 159-190
  7. Teresa H.-Y. Meng
    Pages 191-224
  8. Manavendra Misra, V. K. Prasanna Kumar
    Pages 255-279
  9. Back Matter
    Pages 281-283

About this book

Introduction

Over the past few years, the demand for high speed Digital Signal Proces­ sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni­ tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor­ mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro­ cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac­ ceptable speed performance.

Keywords

Overhead Routing Signal VLSI algorithms communication computer digital signal processor fast Fourier transform (FFT) fault tolerance image processing interconnect network processor radar

Editors and affiliations

  • Magdy A. Bayoumi
    • 1
  1. 1.The University of Southwestern LouisianaUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-3996-4
  • Copyright Information Kluwer Academic Publishers 1991
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6786-4
  • Online ISBN 978-1-4615-3996-4
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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